SDA9189X Datasheet, PDF (23/55 Pages) Siemens Semiconductor Group – Quarter PIP Processor

SDA 9189X
2.4.2 Line Standard of the PIP Picture
The line standard used to display the complete PIP picture is programmable via I²C Bus
(PIPLIN). The line standard of the parent channel or the inset channel can be used. In
addition a fixed line standard of 625 or 525 lines can be chosen.
Combinations of different line standards of the inset signal and the PIP display are
handled in a special way:
PIP display 625 lines, inset signal 525 lines
– The inset picture is shifted down by 12, 8, 6, or 4 lines according to picture size. Due
to this shift the centres of the inset pictures have the same position for both line
standards. The remaining 12, 8, 6, or 4 lines at the top and the bottom of the inset
picture are filled with the luminance value of the full screen background color (BCKY).
The chrominance values are set to ‘0’ for these parts of the inset picture.
PIP display 525 lines, inset signal 625 lines
– The inset picture is reduced to 102, 68, 51, or 34 lines. Depending on the number of
lines the first and the last 12, 8, 6, or 4 lines are omitted. In this way the display shows
the centre part of the original picture.
Displaying multi-PIP pictures this procedure is applied individually to each of the partial
pictures.
2.4.3 Interpolation of the Chrominance Signals
At the memory output the chrominance components are demultiplexed and linearly
interpolated to the luminance sampling rate.
Semiconductor Group
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