SDA9189X Datasheet, PDF (19/55 Pages) Siemens Semiconductor Group – Quarter PIP Processor

SDA 9189X
2.2 Input Signal Processing
2.2.1 Data Transfer
The inset video signal is accepted as digital luminance and chrominance components
with a 13.5 MHz clock for the luminance signal and a 3.375 MHz clock for the
chrominance signals.
Inset synchronization is done via pin HSI for horizontal and pin VSI for vertical
synchronization. By analyzing the synchronization pulses the line standard of the inset
signal source is detected and interference noise on the vertical sync signal is removed.
For applications with fixed line standard (625 lines or 525 lines) the automatic detection
can be switched OFF.
The phase of the vertical sync pulse is programmable (VSIDEL) (see chapter 4.3). This
way a correct detection of the field number is possible, an important condition for frame
mode display.
2.2.2 Decimation Window
A window signal, derived from the sync pulses and the detected line standard, defines
the part of the active video area used for decimation. The window has a width of
576 pixels for the luminance signal and a width of 144 pixels for the chrominance
signals. In the vertical direction the window consists of 252 or 204 lines depending on
the line standard (625 or 525 lines respectively).
The horizontal position of this decimation window can be adapted to various applications
with the help of a programmable delay of the luminance signal (HSIDEL) relative to the
horizontal synchronization pulses. For HSIDEL = ‘0’ the decimation window is opened
0 clock periods (13.5 MHz) after the horizontal synchronization pulse. For the 625 lines
standard the 42th video line is the first decimated line, for the 525 lines standard
decimation starts in the 38th video line.
Semiconductor Group
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03.96