SDA9189X Datasheet, PDF (33/55 Pages) Siemens Semiconductor Group – Quarter PIP Processor

SDA 9189X
Detailed Description
Bit
Name
Function
Subaddress 00
D5
FREEZE
D4
PLLOFF
D3
READ27
D2
LINEDBL
D1
FRAME
D0
PIPON
0: moving picture
1: freeze picture
0: internal PLL ON
1: internal PLL OFF (external clock generation)
0: PIP display with single-read frequency (13.5 MHz)
1: PIP display with double read frequency (27 MHz)
(see note page 31)
0: each line of the PIP memory is read once
(normal operation)
1: each line of the PIP memory is read twice
(line doubling for progressive scan conversion systems
in parent channel)
0: field mode display
1: frame mode display (if possible).
Correct adjustment of bits VSIDEL, VSPDEL required
(see chapter 4.3).
0: PIP insertion OFF
1: PIP insertion ON
Subaddress 01
D6 … D3 SELDEL
D2
VERBLK
D1 … D0 POSHOR
Delay of output signal at pin SEL (– 8 … + 7 periods of read
frequency clock, programmable in 2’s complement code)
0: clamping level at DAC outputs only during line blanking
intervals
1: clamping level at DAC outputs during line blanking
intervals and field-blanking intervals (16 complete lines
following the vertical synchronization pulse of the parent
channel)
2 MSBs of POSHOR (see Subaddress 02 on page 34)
Semiconductor Group
33
03.96