GX4002 Datasheet, PDF (72/74 Pages) Gennum Corporation – Dynamic on-chip power management control

Table 7-1: Configuration and Status Register Map (Continued)
Register Name
Register
Address^d
Parameter Name
CH0PDRATEDET
CH0PDVEYEMON
Bit
Position
Access
0:0
RW
1:1
RW
CH0PWRDN_REG3
RSVD
CH0PDHEYEMON
153
CH0PDPKDET
RSVD
CH0PDCKDIVOUT
RSVD
154
RSVD
CH1PDCH1PATH
2:2
RW
3:3
RW
4:4
RW
5:5
RW
7:6
RW
7:0
RW
0:0
RW
CH1PWRDN_REG0
CH1PWRDN_REG1
CH1PWRDN_REG2
CH1PDCH1CDR*
155
CH1PDCH1CDR
CH1PDCH1SDO
RSVD
156
RSVD
CH1PDLA
RSVD
157
CH1PDLOS
RSVD
CH1PDRATEDET
CH1PDVEYEMON
1:1
RW
2:2
RW
3:3
RW
7:4
RW
7:0
RW
0:0
RW
1:1
RW
2:2
RW
7:3
RW
0:0
RW
1:1
RW
CH1PDHEYEMON
2:2
RW
CH1PWRDN_REG3
158
CH1PDPKDET
3:3
RW
CH1PDDELMON
4:4
RW
CH1PDCKDIVOUT
5:5
RW
RSVD
7:6
RW
RSVD
159
RSVD
7:0
RW
RSVD
160
RSVD
7:0
RW
NOTE: * Indicates bits for lower data rates (below 10G operation)
Reset Value^b
1
1
1
1
1
1
01
00001111
0
0
0
0
0001
00000000
0
1
0
00000
1
1
1
1
1
1
01
00001111
00011111
Valid
Range^d
Function
0-1
0-1
0-1
0-1
0-1
0-1
0-3
0-255
0-1
0-1
0-1
0-1
0-15
0-255
0-1
0-1
0-1
0-31
0-1
0-1
0-1
0-1
0-1
0-1
0-3
0-255
0-255
When HIGH, power-down for rate detector.
When HIGH, power-down for the Ch0 vertical
eye monitor.
When HIGH, power-down for the Ch0
horizontal eye monitor.
When HIGH, power-down for the Ch0 peak
detector.
Reserved. Do not change.
When HIGH, power-down for the divided Ch0
clock divider.
Reserved. Do not change.
Reserved. Do not change.
When HIGH, power-down for the entire Ch1
path.
When HIGH, power-down for the entire CDR.
Valid for below 10G operation.
When HIGH, power-down for the entire CDR.
Valid for 10G to 14G operation.
When HIGH, power-down the trace driver.
Reserved. Do not change.
Reserved. Do not change.
When HIGH, power-down for the LA.
Reserved. Do not change.
When HIGH, power-down for the LOS.
Reserved. Do not change.
When HIGH, power-down for rate detector.
When HIGH, power-down for the Ch1 vertical
eye monitor.
When HIGH, power-down for the Ch1
horizontal eye monitor.
When HIGH, power-down for the Ch0 peak
detector.
When HIGH, power-down for the delay
monitor.
When HIGH, power-down for the divided Ch1
clock divider.
Reserved. Do not change.
Reserved. Do not change.
Reserved. Do not change.
GX4002 2x2 14.025Gb/s Crosspoint Switch with Trace
Equalization and Output De-Emphasis
Data Sheet
55972 - 0
March 2012
72 of 74
Proprietary & Confidential