GX4002 Datasheet, PDF (14/74 Pages) Gennum Corporation – Dynamic on-chip power management control

3. Using on-chip automatic rate detection circuitry to detect the new data rate, and to
invoke an internal rate select in either the Ch1 or Ch0 path independently. The
application is defined using the RATEDETFCGBEN bits (CH1PLLRATESELVAL is
LOW and/or CH0PLLRATESELVAL is LOW).
Rate
Selection
Method
Hard Rate
Select
Soft Rate
Select
Automatic
Rate
Detect
Rate
Select
Valid
Register
HIGH
HIGH
LOW
RS0/RS1
Pins
Rate
Select
Registers
Fibre
Channel/
Ethernet
Register
Operation
Data Rate
Dependent
Register Set Used
LOW
HIGH
Low or
High Z
Not
Applicable
Not
Applicable
LOW
Not
Applicable
LOW
High
Not
Applicable
Not
Applicable
Fibre
Channel
Ethernet
Not
Applicable
Fibre
Channel
Ethernet
The CDRs are placed in bypass
mode. Intended for 2G/4G/8G Fibre
Channel or 1GbE
The CDR will lock to 14.025Gb/s
data
The CDR will lock to 9.95G to
11.3Gb/s data
The CDRs are place in bypass mode.
Intended for 2G/4G/8G Fibre
Channel or 1GbE
The CDR will lock to 14.025Gb/s
data
The CDR will lock to 9.95G to
11.3Gb/s data
Fibre
Channel
If the input data is 14.025Gb/s, the
CDR will lock to it. Otherwise, the
CDRs are automatically bypassed
Ethernet
If the input data is 9.95G to 11.3G,
the CDR will lock to it. Otherwise,
the CDRs are automatically
bypassed
Low Data Rate
Profile
High Data Rate
Profile
High Data Rate
Profile
Low Data Rate
Profile
High Data Rate
Profile
High Data Rate
Profile
If 14.025Gb/s is
detected: High Data
Rate Profile
If 14.025Gb/s is not
detected: Low Data
Rate Profile
If 9.95G to 11.3Gb/s
is detected: High
Data Rate Profile
If 9.95G to 11.3Gb/s
is not detected: Low
Data Rate Profile
3.1.1.1 Hard Rate Select (Rate Select Pins)
The RS0 pin controls the rate-dependent profile of the Ch0 path, and the RS1 pin
controls the rate-dependent profile of the Ch1 path. The rate select valid bit,
CH0PLLRATESELVAL (or CH1PLLRATESELVAL), must be HIGH for RS0 (or RS1) to
control the rate.
When the RS0 (or RS1) pin is held LOW, the low-speed rate-dependent registers of the
channel 0 (or channel 1) path are active. When the RS0 (or RS1) pin is held HIGH, the
high-speed rate-dependent profile of the channel 0 (or channel 1) path is active. RS0 is
logically OR'ed with CH0PLLRATESEL, while RS1 is logically OR'ed with
CH1PLLRATESEL. Due to the OR'ing operation, when RS0 and RS1 are used for rate
control, CH0PLLRATESEL and CH1PLLRATESEL must be set LOW.
GX4002 2x2 14.025Gb/s Crosspoint Switch with Trace
Equalization and Output De-Emphasis
Data Sheet
55972 - 0
March 2012
14 of 74
Proprietary & Confidential