GX4002 Datasheet, PDF (51/74 Pages) Gennum Corporation – Dynamic on-chip power management control

3.9.3 I/O and Register States During and After Reset
All configuration registers are set to their post-reset defaults state immediately
following RESET assertion.
The following I/O states are applicable upon RESET assertion:
Table 3-10: I/O and Register States During and After Reset
Pin Name
SDA
SCL
Ch0FAULT
Ch1LOS
I/O State upon RESET Assertion
This pin is configured as an input while RESET is asserted and
immediately following RESET negation. When configured as an
input, this pin is high-impedance.
This pin is configured as an input while RESET is asserted, and
immediately following RESET negation. When configured as an
input, this pin is high-impedance.
This pin is configured as an open-drain output while RESET is
asserted and immediately following RESET negation.
This output will be high-impedance, and its state will depend on
the external pull-up.
This pin is configured as an open-drain output while RESET is
asserted and immediately following RESET negation. If a signal
is present, the output will be pulled LOW. Otherwise, this output
will be high-impedance and it’s state will depend on the
external pull-up.
3.10 Digital Control Interface
The GX4002 has a serial control interface to communicate with the part. An I²C protocol
can be used.
3.10.1 I²C Host Interface Mode
The I²C mode supports standard-mode (100kb/s) and fast-mode (400kb/s) signalling.
The device only supports slave mode. The pins SDA and SCL are used for bi-directional
serial data and clock respectively.
The GX4002 device slave address is 24h (= 0100100x).
The I²C protocol is implemented as per the following description:
Each access begins with a 7-bit I²C slave address word, an 8-bit register address word,
followed by two 8-bit data words written to, or read from, the GX4002.
GX4002 2x2 14.025Gb/s Crosspoint Switch with Trace
Equalization and Output De-Emphasis
Data Sheet
55972 - 0
March 2012
51 of 74
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