GX4002 Datasheet, PDF (71/74 Pages) Gennum Corporation – Dynamic on-chip power management control

Table 7-1: Configuration and Status Register Map (Continued)
Register Name
ADC_REG0
Register
Address^d
Parameter Name
ADCRESET
ADCAUTOCONVEN
ADCJUSTLSB
142
ADCOFFMODE
Bit
Position
Access
0:0
RW
1:1
RW
2:2
RW
3:3
RW
ADC_REG1
ADC_REG2
ADC_REG3
ADC_REG4
ADC_REG5
ADC_REG6
ADC_REG7
ADC_REG8
RSVD
ADCSRCSEL
143
ADCOFFCALEN
ADCRESOLUTION
144
ADCCLKRATE
RSVD
ADCSTARTCONV
145
RSVD
ADCDONECONV
146
RSVD
147
ADCOUTLO
148
ADCOUTHI
149
ADCOFFSETLO
150
ADCOFFSETHI
CH0PDCH0PATH
7:4
RW
3:0
RW
7:4
RW
2:0
RW
5:3
RW
7:6
RW
0:0
RW
7:1
RW
0:0
RO
7:1
RW
7:0
RO
7:0
RO
7:0
RW
7:0
RW
0:0
RW
CH0PWRDN_REG1
CH0PDCH0CDR*
151
CH0PDCH0CDR
1:1
RW
2:2
RW
CH0PDCH0SDO
3:3
RW
RSVD
7:4
RW
CH0PDEQ
0:0
RW
CH0PWRDN_REG2
152
CH0PDLOS
1:1
RW
RSVD
7:2
RW
NOTE: * Indicates bits for lower data rates (below 10G operation)
Reset Value^b
1
1
1
0
0000
0000
0000
001
101
00
0
0000000
0
0000000
00000000
00000000
00000000
00000000
0
0
0
1
0010
0
0
100000
Valid
Range^d
Function
0-1
0-1
0-1
0-1
0-15
0-15
0-15
0-7
0-7
0-3
0-1
0-127
0-1
0-127
0-255
0-255
0-255
0-255
0-1
0-1
0-1
0-15
0-1
0-1
0-63
Reset for the ADC.
When HIGH, enables auto conversion. Set LOW
for manual.
When HIGH, justify towards LSB. LOW justifies
towards MSB.
When LOW, offset is subtracted from the ADC
output. When HIGH, offset is added to the ADC
output.
NOTE: When HIGH, ADCOFFSETHI[7] is sign and
rest of the bits are magnitude. A sign value of 1
represents negative numbers.
Reserved. Do not change.
Select input for ADC (see Section 3.7.1).
Select source for offset calibration.
ADC resolution control: 0-7 -> 4b to 16b.
ADC clock divide ratio.
Reserved. Do not change.
ADC start conversion.
Reserved. Do not change.
ADC conversion done flag.
Reserved. Do not change.
ADC output LOW MSB.
ADC output HIGH MSB.
ADC offset LSB, unsigned binary.
ADC offset MSB, unsigned binary
When HIGH, power-down for the entire Ch0
path.
When HIGH, power-down for the entire CDR.
Valid for below 10G operation.
When HIGH, power-down for the entire CDR.
Valid for 10G to 14G operation.
When HIGH, power-down for the entire driver.
Reserved. Do not change.
When HIGH, power-down for the equalizer.
When HIGH, power-down for the LOS.
Reserved. Do not change.
GX4002 2x2 14.025Gb/s Crosspoint Switch with Trace
Equalization and Output De-Emphasis
Data Sheet
55972 - 0
March 2012
71 of 74
Proprietary & Confidential