GX4002 Datasheet, PDF (7/74 Pages) Gennum Corporation – Dynamic on-chip power management control

Table 1-1: Pin Descriptions (Continued)
Pin #
27
28
29
30, 31
Name
VREG
DIGVSS
RS0
SDO0,
SDO0
32
Ch0FAULT
Type
Passive
Ground
Digital
Input
Output
Digital
Output
Description
LDO regulator capacitor connection. (1.8V)
Ground for low-speed digital I/O and internal logic.
Input Digital LVTTL/LVCMOS-compliant input.
Rate Select Input for the Ch0 Signal Path.
See Section 3.1 Multirate CDR Functionality for more details.
High-speed differential output for the channel 0 signal path.
SFP+-compliant active-high digital output. Open-collector Ch0FAULT indicator. Requires
an external pull-up resistor.
When Ch0FAULT is LOW, the channel 0 path output is operating properly.
When Ch0FAULT is high-impedance, the device has detected a fault condition.
The Ch0FAULT is latched, and may be cleared via the host interface or by strobing the
Ch0DSBL pin.
Can be configured as a LVTTL/LVCMOS compatible output.
GX4002 2x2 14.025Gb/s Crosspoint Switch with Trace
Equalization and Output De-Emphasis
Data Sheet
55972 - 0
March 2012
7 of 74
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