GX4002 Datasheet, PDF (52/74 Pages) Gennum Corporation – Dynamic on-chip power management control

S I ²C Slave Address W A
register address
A
register’s data
Single 8-bit-Register Write Cycle - Over I ²C Bus
AP
Legend:
From Master to Slave
From Slave to Master
A = Acknowledge (SDA LOW)
N = No Acknowledge (SDA HIGH)
S = Start Condition
Sr = Restart Condition
P = Stop Condition
R = Read mode (=1)
W = Write mode (=0)
Figure 3-26: Single Register Write Cycle over I²C Bus
S
I ²C Slave Address W A
register address
A Sr I ²C Slave Address
RA
Single 8-bit-Register Read Cycle - Over I² C Bus
register’s data
NP
Legend:
From Master to Slave
From Slave to Master
A = Acknowledge (SDA LOW)
N = No Acknowledge (SDA HIGH)
S = Start Condition
Sr = Restart Condition
P = Stop Condition
R = Read mode (=1)
W = Write mode (=0)
Figure 3-27: Single Register Read Cycle over I²C Bus
S
I ²C Slave Address W A register address (RA) A
data (RA)
A
data (RA + 1)
A
data (RA + 2)
A
A
data (RA + n - 4)
A
data (RA + n - 3)
A
data (RA + n - 2)
A
data (RA + n - 1)
AP
Multiple 8-bit-Registers (consecutive address) Write Cycle - Over I ²C Bus
Legend:
From Master to Slave
From Slave to Master
A = Acknowledge (SDA LOW)
N = No Acknowledge (SDA HIGH)
S = Start Condition
Sr = Restart Condition
P = Stop Condition
R = Read mode (=1)
W = Write mode (=0)
Figure 3-28: Bulk Register Write Cycle over I²C Bus
S I ²C Slave Address W A register address (RA) A Sr I ²C Slave Address
RA
data (RA)
A
A data (RA + n - 4)
A
data (RA + n - 3)
A
data (RA + n - 2)
A
Multiple Registers (consecutive address) Read Cycle - Over I²C Bus
data (RA + n - 1)
NP
Legend:
From Master to Slave
From Slave to Master
A = Acknowledge (SDA LOW)
N = No Acknowledge (SDA HIGH)
S = Start Condition
Sr = Restart Condition
P = Stop Condition
R = Read mode (=1)
W = Write mode (=0)
Figure 3-29: Bulk Register Read Cycle over I²C Bus
GX4002 2x2 14.025Gb/s Crosspoint Switch with Trace
Equalization and Output De-Emphasis
Data Sheet
55972 - 0
March 2012
52 of 74
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