GX4002 Datasheet, PDF (34/74 Pages) Gennum Corporation – Dynamic on-chip power management control

3.6.1 PRBS Generator and Checker
The GX4002 has a built in PRBS7 generator and checker. The generator and checker are
disabled by default to save power, and can be enabled through the digital control
interface. There are multiple ways to use the PRBS generator/checker, as shown in
Table 3-9 below:
Table 3-9: PRBS Generator/Checker Modes of Operation
Mode
Lock to data pattern on Ch1 input
Lock to data pattern on Ch0 input
Lock to low-speed reference on
Ch1 input
Lock to low-speed reference on
Ch0 input
Description
A data pattern, such as PRBS data or Fibre Channel/10GbE traffic, can be sent to the Ch1 path
input. A PRBS7 pattern can be viewed at the Ch1 path output, or can be looped back to the
Ch0 side to use the PRBS checker.
A data pattern, such as PRBS data or Fibre Channel/10GbE traffic, can be sent to the Ch0 path
input. A PRBS7 pattern can be viewed at the Ch0 path output, or can be looped back to the
Ch1 side to use the PRBS checker.
A reference at 1/8 (14G) or 1/4 (10G) of the desired rate can be sent to the Ch1 input. A PRBS7
pattern can be viewed at the Ch1 path output, or can be looped back to the Ch0 side to use
the PRBS checker. This mode can be used when testing a module so that high-speed test
equipment is not required. See Figure 3-17.
A reference at 1/8 (14G) or 1/4 (10G) of the desired rate can be sent to the Ch0 input. A PRBS7
pattern can be viewed at the Ch0 path output, or can be looped back to the Ch1 side to use
the PRBS checker. This mode can be used when testing a module so that high-speed test
equipment is not required. See Figure 3-18.
Recovered
Clock
HEye Monitor
Ch0 CDR (10G/14G)
Retimed
Data
Input
Data
LBCH0INEN = 0
0
1
Peak
Detector
VEye
Monitor
Ch0 EQ
PRBS Out
SDO0
Ch0 Driver
fclk/8 (14G)
fclk/4 (10G)
SDI1
Peak
Detector
VEye
Monitor
Ch1 LA
LBCH0OUTEN = 0
0
0
1
1
CH0PLLPOLINV
CH0PLLBYPASS = 0 0
1
PRBSCHKCLKSEL = 1
Ch0Clk
PRBS 7
Generator
PRBS 7
Checker
Ch1Clk
1
0
LBCH1OUTPRBSGEN = 1
0
1
CH1PLLPOLINV
1
0 _{Ch1 Driver}
0
1
LBCH1OUTEN = 1
1
0
LBCH1INEN = 0
Input
Data
Retimed
Data
Ch1 CDR (10G/14G)
HEye Monitor
Recovered
Clock
PRBSGENCLKSEL = 0
High-speed Data
High-speed Clock
Low-speed Reference
SDO1
Figure 3-17: PRBS Generator on Ch1 Output and PRBS Check Monitoring Ch0 Input
SDI0
External
Loopback
GX4002 2x2 14.025Gb/s Crosspoint Switch with Trace
Equalization and Output De-Emphasis
Data Sheet
55972 - 0
March 2012
34 of 74
Proprietary & Confidential