LC822973 Datasheet, PDF (8/27 Pages) Sanyo Semicon Device – CMOS LSI TV Image Viewer LSI

LC822973
This LSI consists of 9 function blocks in the structure block above.
(1) CPU interface (CPUIF BLOCK)
The parameter setup such as mode setup/image area setup/video encoder characteristic of this LSI is possible via
bus from CPU. The image data writing to SDRAM achieves image port writing command that is in the same
command class as regular register and the same command class and keep writing continuously. This is a double
bank buffer structure and is able to write drawing data for 1 line without WAIT control.
(2) Host access (HOST ACCESS BLOCK)
The image writing is fulfilled from CPU interface for SDRAM.
This obtains line buffer in double bank buffer and the writing is carried out to SDRAM as accessing from CPU. It
also mounts 90, 180, 270 degrees rotation writing and writing function with matrix conversion processing besides
regular writing.
(3) SDRAM control (DRAM CONTROL BLOCK)
This LSI is MCP (multi chip) structure and has 16Mbit SDRAM built-in. This is the memory controller that controls
writing from CPU, reading for real-time display to video encoder and refresh processing for this memory.
(4) Reading control for display (DISPLAY ACCESS BLOCK)
This is the SDRAM reading processing part that controls transferring real-time image data to NTSC/PAL video
encoder.
This consists of scaling part that performs enlargement processing for image data that was read from SDRAM and
the buffer controlling part that provides video signal continuously to video encoder. The background processing
circuit that inserts fixed level is mounted in the buffer control part besides display window (image from SDRAM).
(5) Video encoder (VIDEO ENCODER BLOCK)
This supports both NTSC/PAL methods. All timing signals that are necessary for video signal are generated in this
block. This operates as a sync master and generates transfer request of real-time image data for DISPLAY ACCESS
BLOCK.
(6) Video interface (VIDEOIF BLOCK)
It is an interface part for the video rate writing. It writes based on a video sync signal and the dot clock. In case of
RGB format (RGB565, RGB666 etc.), the image is input to the host access part by processing the matrix at valid
period. The BT656 decoding is done if necessary at the YUV format. it supports both non-interlace and interlace
format. When the video interface is used, the data bus (D15 - D0) is treated as a dedicated image bus. The command
issue and the register access are executed with the I²C bus. It has the I²C bus control part in CPU interface part.
(7) Automatic image viewing (AUTOVIEW CONTROL BLOCK)
Automatic writing/reading sequence is executed by alternating the pre-defined image banks. Thus clean images
without the scan passing (tearing image) are displayed. Consecutive image data transfer follows after one time
command and parameter setting.
(8) VBI control (VBI CONTROL BLOCK)
The CGMS-A/WSS data is inserted. It has AUX function for the copy protect control etc.
(9) Others
To combine drawing from CPU and real-time request (continuous video signal is provided to NTSC/PAL video
encoder), SDRAM needs to be operated with high-speed clock. The high-speed master clock (MCLK) is created and
supported by using PLL for input clock (CKI).
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