LC822973 Datasheet, PDF (19/27 Pages) Sanyo Semicon Device – CMOS LSI TV Image Viewer LSI

LC822973
I²C access
When video I/F is used (USEVIF==1), the register access from the host uses the I²C bus.
One sending data size of the I²C bus is 8bit.
Additionally, I²C is not applicable the concept of the address (A0==0: the command and A0==1: parameter) used with
parallel CPUIF.
Therefore, a special access way is necessary as follows respectively.
Stand-alone command : not need parameter--IMGWRITE,IMGREADGO etc.)
write "00" into the target address
target address+"00"
(normal write : need 1word parameter)
write sequentially "upper byte" → "lower byte" into target address.
address is "upper : normal address×2" , "lower : normal address×2+1" in case of I²C.
target address(upper)+"writing data for upper byte"
target address(lower)+"writing data for lower byte"
*Please keep the order "upper byte → lower byte".
When the host accessing is finished, internal transfer with word align will start.
(normal read : need 1word parameter)
read sequentially "upper byte" → "lower byte" from target address.
address is "upper : normal address×2" , "lower : normal address×2+1" in case of I²C.
target address(upper)+"reading data for upper byte"
target address(lower)+"reading data for lower byte"
The read order from upper byte or lower byte doesn't especially have regulations.
Only one byte accessing is also possible.
(image writing command : AUTOVIEWON,IMGWRITE,OSDWRITE etc.)
write via special image port (IMGPORT : 0×FD).
After issuing the image writing command, the data writing is necessary
in accurate the order. (upper → lower → upper → lower...)
On the other hand, the data writing operation from the host is unnecessary
because the automatic writing is done with a pin (image data/dot clock) at video IF.
target address+"00" ← Issue AUTOVIEWON command etc.
IMGPORT address+"data writing for upper byte : at 1st pixel"
IMGPORT address+"data writing for lower byte : at 1st pixel"
IMGPORT address+"data writing for upper byte : at 2nd pixel"
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IMGPORT address+"data writing for upper byte : at Nth pixel"
IMGPORT address+"data writing for lower byte : at Nth pixel"
(image reading command : IMGREAD)
read via special image port (IMGPORT : 0×FD).
The access order is same as parallel CPU IF : IMGREADGO → IMGREAD → image reading.
IMGREADGO+"00" ← Issue IMGREADGO command.
IMGREAD+"00" ← Issue IMGREAD command.
IMGPORT address+"reading target pixel's upper byte"
IMGPORT address+"reading target pixel's lower byte"
Please keep the order "upper byte → lower byte".
Because the I²C bus is low-speed, status read after IMGREADGO command is unnecessary.
(status read :)
Status and a usual register are distinguished referring to the A0 address at parallel IF.
On the other hand, it corresponds in a special address in I²C.
(STAT upper : STATUP : 0×FE, STAT lower : STATDN : 0×FF).
STATUP address+"reading upper byte of STATUS register"
STATDN address+"reading upper byte of STATUS register"
The read order from upper byte or lower byte doesn't especially have regulations.
Only one byte accessing is also possible.
No.A2131-19/27