LC822973 Datasheet, PDF (22/27 Pages) Sanyo Semicon Device – CMOS LSI TV Image Viewer LSI

AC characteristics (CPU bus timing)
LC822973
Parallel I/F (I80 like)
A
CPU WRITE
CS
twas twah
twcs twch
twlw
twhw
/WR
tcycw
/RD
high
twds twdh
Data
CPU READ
A
CS
/WR
/RD
Data
tras trah
trcs trch
trlw
trhw
tcycr
tacc
trdh
Item
System cycle time (write) [×1 transfer]
System cycle time (read) [×1 transfer]
System cycle time (write) [×2, ×3 transfer]
System cycle time (read) [×2, ×3 transfer]
Address setup time (write)
Address hold time (write)
Address setup time (read)
Address hold time (read)
CS setup time (write)
CS hold time (write)
CS setup time (read)
CS hold time (read)
/WR low side pulse width
/WR high side pulse width
/RD low side pulse width
/RD high side pulse width
Data setup time
Data hold time
Read access time
Data hold time
Symbol
tcycw
tcycr
tcycw
tcycr
twas
twah
tras
trah
twcs
twch
trcs
trch
twlw
twhw
trlw
trhw
twds
twdh
tacc*
Trdh
Condition
write
read
write
read
A
A
A
A
/CS
/CS
/CS
/CS
/WR
/WR
/RD
/RD
Data [15:0]
Data [15:0]
Data [15:0]
Data [15:0]
* T ⇒ MCLK (master clock) 1 cycle .ex. MCLK: 50MHz ⇒ 1T is 20ns.
*tacc ⇒ from (/RD) or (/CS)↓
high
min
typ
3T*
3T*
2T*
2T*
15
5
25
5
15
5
25
5
20
15
25
15
15
5
max
unit
cyc
cyc
cyc
cyc
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
20
ns
10
ns
No.A2131-22/27