LC822973 Datasheet, PDF (15/27 Pages) Sanyo Semicon Device – CMOS LSI TV Image Viewer LSI

Peripheral Circuit Example
LC822973
use at 18bit mode.
"0"-command
monitor pin
open
setting
OSC
System
Reset
DB17
DB16
D15-0
A0
CS
WR
RD
INT
MON
SDA
SCL
MODE2-0
CONF3-0
CKI
XRST
LC822973
via CPUIF
use at 18bit mode.
VIFVD
VIFFI
VIFHS
VIFVS
VIFDOT
VIFVACT
VIFHACT
DB17
DB16
D15-0
CS
WR
RD
CONF3
CONF2
CONF1
CONF0
I²C
needed
pullup
IDSEL(choose ID)
SDA
SCL
monitor pin
setting
A0
SDA
SCL
INT
MON
MODE2-0
LC822973
OSC
System
Reset
CKI
XRST
via VIDEOIF
DACOUT
IOB
An example of LPF
3.3μH
L
330pF
330pF
"AVSS" "AVSS"
LPF
CVBS
100μF--220μF
Recommendation:
220μF
COMP
VREF
IREF
1μF AVDD
0.1μF
DAC Analog
560Ω AVSS
100--150Ω
VCNT
0.1μF--0.22μF
PLL Analog
DACOUT
IOB
An example of LPF
3.3μH
L
330pF
330pF
"AVSS" "AVSS"
LPF
CVBS
100μF--220μF
Recommendation:
220μF
COMP
VREF
IREF
1μF AVDD
DAC Analog
0.1μF
560Ω ^AVSS
100--150Ω
VCNT
0.1μF--0.22μF
PLL Analog
* The MODE2:0 pins are for test use, so please tie them "L".
* Please do not leave input pins OPEN.
* Above figure shows in case of 27MHz (24.54MHz) clock input.
When the dot clock is generated with PLL (.e.g.: CKI==26MHz), it is necessary to change in PLL loop filter's
constant. Please refer to " 7.12. Consideration of 26.0MHz clock input" paragraph for details.
No.A2131-15/27