LC822973 Datasheet, PDF(20/27 Page) Sanyo Semicon Device

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LC822973 Datasheet, PDF (20/27 Pages) Sanyo Semicon Device – CMOS LSI TV Image Viewer LSI

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LC822973

List of Command (A0==0)

The following tables are memory maps for 16bitCPU bus with 16bit width parameters.

I2C takes Big ENDIAN system.

upper byte : I2C_address = Add Ã 2

lower byte : I2C_address = Add Ã 2 + 1

Add

Command name

1 0Ã01 CLKCONT

2 0Ã02 DIV_M

3 0Ã03 DIV_N

4 0Ã04 DIV_P

5 0Ã05 reserved

6 0Ã06 INT

7 0Ã07 INTEN

8 0Ã08 SYSCTL1

9 0Ã09 SYSCTL2

10 0Ã0a SYSCTL3

11 0Ã0b MEMSET1

12 0Ã0c MEMSET2

13 0Ã0d MEMSET3

14 0Ã0e IMGWRITE

15 0Ã0f

IMGREADGO

16 0Ã10 IMGREAD

17 0Ã11 IMGABORT

18 0Ã12 SCALE

19 0Ã13 reserved

20 0Ã14 reserved

21 0Ã15 WFBHLEN

22 0Ã16 WFBVLEN

23 0Ã17 WFBHSTART

24 0Ã18 WFBVSTART

25 0Ã19 RFBHOFST

26 0Ã1a RFBVOFST

27 0Ã1b DSPHOFST

28 0Ã1c DSPVOFST

29 0Ã1d DSPHLEN

30 0Ã1e DSPVLEN

31 0Ã1f

BGCOLOR1

32 0Ã20 BGCOLOR2

33 0Ã21 ENCMODE

34 0Ã22 ENCGAIN1

35 0Ã23 ENCGAIN2

36 0Ã24 ENCBST1

37 0Ã25 ENCBST2

38 0Ã26 ENCBBPLT

39 0Ã27 ENCRHVAL

40 0Ã28 ENCHBLK

41 0Ã29 ENCVBLK

42 0Ã2a VERSION

43 0Ã2b TESTMODE

44 0Ã2c OSDCONT_1

Function

Clock control

PLL control

Interrupt

System setup

MEMCTL setup

CPU drawing

Image reading

Drawing end

Scale up

Coordinate setup

Background color

VENC setup

Video timing

Other

For test

OSD1 setup

length

1word

Description

VCLK_MODE, PLLON, DACON, DRAM sleep, Mode setting at

VIDEOIF

1/M (12bit)

1/N (12bit)

1/P (8bit), S0--S3

INT factor

*) this can be issued during memory writing

INT factor clear

*) this can be issued during memory writing

Scaler and Matrix ON/OFF, scan direction, display OFF, filter

setup, enhancer setup, etc.

Transfer mode setup, V sync setup, etc.

Polarity, system control, etc. (others, spare)

SDRAM burst length, latency, mode, etc.

SDRAM refresh interval

SDRAM initial sequence setup

CPU â SDRAM Writing

SDRAM â CPU Reading start

SDRAM â CPU Reading (acquiring data)

CPU drawing forced termination

Scaling image ratio setup

SDRAM address length for CPU drawing (H)

SDRAM address length for CPU drawing (V)

horizontal start point for SDRAM writing

vertical start point for SDRAM writing

Real-time reading SDRAM address offset (H)

Real-time reading SDRAM address offset (V)

Real-time reading display position offset (H)

Real-time reading display position offset (V)

Real-time reading display position length (H)

Real-time reading display position length (V)

Background color Y signal (use only low 8bit)

Background color UV signal (U: upper, V: lower)

Operation mode, filter switch, interlace setup

Level setup, bright, contrast

Level setup, color gain

Burst gain setup

Burst phase setup

Blueback pallet setup

Horizontal valid period signal to the memory controller

adjustment

Horizontal Blanking period adjustment

Vertical Blanking period adjustment

Version register

SDRAM burst length,OSD1 ON/OFF, etc.

Continued to the next page.

No.A2131-20/27

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