K4E170811D Datasheet, PDF (7/21 Pages) Samsung semiconductor – 2M x 8Bit CMOS Dynamic RAM with Extended Data Out

K4E170811D, K4E160811D
K4E170812D, K4E160812D
TEST MODE CYCLE
Parameter
Random read or write cycle time
Read-modify-write cycle time
Access time from RAS
Access time from CAS
Access time from column address
RAS pulse width
CAS pulse width
RAS hold time
CAS hold time
Column address to RAS lead time
CAS to W delay time
RAS to W delay time
Column address to W delay time
CAS precharge to W delay time
Hyper Page cycle time
Hyper Page read-modify-write cycle time
RAS pulse width (Hyper Page cycle)
Access time from CAS precharge
OE access time
OE to data delay
OE command hold time
Symbol
tRC
tRWC
tRAC
tCAC
tAA
tRAS
tCAS
tRSH
tCSH
tRAL
tCWD
tRWD
tAWD
tCPWD
tHPC
tHPRWC
tRASP
tCPA
tOEA
tOED
tOEH
-50
Min
Max
89
121
55
18
30
55
10K
13
10K
18
43
30
35
72
47
52
25
53
55
200K
33
18
18
18
CMOS DRAM
-60
Min
Max
109
145
65
20
35
65
10K
15
10K
20
50
35
39
84
54
59
30
61
65
200K
40
20
20
20
( Note 11 )
Units Note
ns
ns
ns 3,4,10,12
ns 3,4,5,12
ns
3,10,12
ns
ns
ns
ns
ns
ns
7
ns
7
ns
7
ns
ns
13
ns
13
ns
ns
3
ns
ns
ns