K4E170811D Datasheet, PDF (6/21 Pages) Samsung semiconductor – 2M x 8Bit CMOS Dynamic RAM with Extended Data Out

K4E170811D, K4E160811D
K4E170812D, K4E160812D
AC CHARACTERISTICS (Continued)
Parameter
Symbol
Data set-up time
Data hold time
Refresh period (2K, Normal)
Refresh period (4K, Normal)
Refresh period (L-ver)
Write command set-up time
CAS to W delay time
RAS to W delay time
Column address to W delay time
CAS precharge to W delay time
CAS set-up time (CAS -before-RAS refresh)
CAS hold time (CAS -before-RAS refresh)
RAS to CAS precharge time
Access time from CAS precharge
Hyper Page cycle time
Hyper Page read-modify-write cycle time
CAS precharge time (Hyper Page cycle)
RAS pulse width (Hyper Page cycle)
RAS hold time from CAS precharge
OE access time
OE to data delay
Output buffer turn off delay time from OE
OE command hold time
Write command set-up time (Test mode in)
Write command hold time (Test mode in)
W to RAS precharge time(C-B-R refresh)
W to RAS hold time(C-B-R refresh)
Output data hold time
Output buffer turn off delay from RAS
Output buffer turn off delay from W
W to data delay
OE to CAS hold time
CAS hold time to OE
OE precharge time
W pulse width (Hyper Page Cycle)
RAS pulse width (C-B-R self refresh)
RAS precharge time (C-B-R self refresh)
CAS hold time (C-B-R self refresh)
tDS
tDH
tREF
tREF
tREF
tWCS
tCWD
tRWD
tAWD
tCPWD
tCSR
tCHR
tRPC
tCPA
tHPC
tHPRWC
tCP
tRASP
tRHCP
tOEA
tOED
tOEZ
tOEH
tWTS
tWTH
tWRP
tWRH
tDOH
tREZ
tWEZ
tWED
tOCH
tCHO
tOEP
tWPE
tRASS
tRPS
tCHS
-50
Min
Max
0
8
32
64
128
0
30
67
42
47
5
10
5
28
20
47
8
50
200K
30
13
13
3
13
13
10
10
10
10
5
3
13
3
13
15
5
5
5
5
100
90
-50
CMOS DRAM
-60
Min
Max
0
10
32
64
128
0
34
79
49
54
5
10
5
35
25
56
10
60
200K
35
15
15
3
15
15
10
10
10
10
5
3
15
3
15
15
5
5
5
5
100
110
-50
Units Notes
ns
9
ns
9
ms
ms
ms
ns
7
ns
7
ns
7
ns
7
ns
ns
ns
ns
ns
3
ns
13
ns
13
ns
ns
ns
ns
ns
ns
6
ns
ns
11
ns
11
ns
ns
ns
ns
6,14
ns
6
ns
ns
ns
ns
ns
us 15,16,17
ns 15,16,17
ns 15,16,17