K4E170811D Datasheet, PDF (5/21 Pages) Samsung semiconductor – 2M x 8Bit CMOS Dynamic RAM with Extended Data Out

K4E170811D, K4E160811D
K4E170812D, K4E160812D
CMOS DRAM
CAPACITANCE (TA=25°C, VCC=5V or 3.3V, f=1MHz)
Parameter
Symbol
Min
Input capacitance [A0 ~ A11]
CIN1
-
Input capacitance [RAS, CAS, W, OE]
CIN2
-
Output capacitance [DQ0 - DQ7]
CDQ
-
Max
Units
5
pF
7
pF
7
pF
AC CHARACTERISTICS (0°C≤TA≤70°C, See note 1,2)
Test condition (5V device) : VCC=5.0V±10%, Vih/Vil=2.4/0.8V, Voh/Vol=2.0/0.8V
Test condition (3.3V device) : VCC=3.3V±0.3V, Vih/Vil=2.0/0.8V, Voh/Vol=2.0/0.8V
Parameter
Symbol
Random read or write cycle time
Read-modify-write cycle time
Access time from RAS
Access time from CAS
Access time from column address
CAS to output in Low-Z
Output buffer turn-off delay from CAS
OE to output in Low-Z
Transition time (rise and fall)
RAS precharge time
RAS pulse width
RAS hold time
CAS hold time
CAS pulse width
RAS to CAS delay time
RAS to column address delay time
CAS to RAS precharge time
Row address set-up time
Row address hold time
Column address set-up time
Column address hold time
Column address to RAS lead time
Read command set-up time
Read command hold time referenced to CAS
Read command hold time referenced to RAS
Write command hold time
Write command pulse width
Write command to RAS lead time
Write command to CAS lead time
tRC
tRWC
tRAC
tCAC
tAA
tCLZ
tCEZ
tOLZ
tT
tRP
tRAS
tRSH
tCSH
tCAS
tRCD
tRAD
tCRP
tASR
tRAH
tASC
tCAH
tRAL
tRCS
tRCH
tRRH
tWCH
tWP
tRWL
tCWL
-50
Min
Max
84
116
50
13
25
3
3
13
3
2
50
30
50
10K
13
38
8
10K
20
37
15
25
5
0
10
0
8
25
0
0
0
10
10
13
8
-60
Min
Max
104
140
60
15
30
3
3
15
3
2
50
40
60
10K
15
45
10
10K
20
45
15
30
5
0
10
0
10
30
0
0
0
10
10
15
10
Units Notes
ns
ns
ns
3,4,10
ns
3,4,5
ns
3,10
ns
3
ns
6,14
ns
3
ns
2
ns
ns
ns
ns
ns
ns
4
ns
10
ns
ns
ns
ns
ns
ns
ns
ns
8
ns
8
ns
ns
ns
ns