DS_S1D2502A01 Datasheet, PDF (52/57 Pages) Samsung semiconductor – VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS

Preliminary
VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS
S1D2502A01
• HF Bits Selection
HF bits is not selecting from out of 8 (2³) steps uniformly, but selecting the step shown in figure below. In
example, at 800 mode, there are 5 steps that the frequency range is controlled by HF bits.
Table 16. HF Bits Selection
DIV
DOT1
DOT0
HF2
HF1
HF0
320
0
0
480
0
1
640
1
0
800
1
1
After fixing time constants of the external circuit and PLL control bits except HF bits, if HF bits are stepped up, the
voltage measured at pin-3 drops. On the contrary, if HF bits are stepped down, the voltage rises.
The voltage measured at pin-3 don't change by changing CP bits.
• External Register at pin-4
The external register at pin-4 is the factor that changes greatly at PLL tunning. The initial value of this external
register value is decided as follows.
At first, the external register is replaced variable-register (about 50KΩ range).
and then, set the lowest PLL control bits at the lowest frequency allowed by set.
and then, change variable-register to be 2.35V that optimum voltage is locking.
and then, measure register value at this time.
also, set the highest PLL control bits at the highest frequency allowed by set.
and then, change variable-register to be 2.35V that optimum voltage is locking.
and then, measure register value at this time.
You may decide the average of these two registers' value to initial value.
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