DS_S1D2502A01 Datasheet, PDF (47/57 Pages) Samsung semiconductor – VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS

S1D2502A01
Preliminary
VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS
PLL CONTROL
• Introduction
PLL (Phase Lock Loop) is feedback controlled circuit that maintains a constant phase difference between a
reference signal and an oscillator output signal.
Generally, PLL is composed as follow Figure.
Reference Signal
PFD
(Phase Frequency Detector)
LF
(Loop Filter)
FD
(Frequency Detector)
VCO (Voltage
Controlled Oscillator)
Figure 22. Block Diagram of General PLL
- PFD (Phase Frequency Detector)
PFD compares the phase of the VCO output frequency, with the phase of a reference signal frequency output
pulse is generated in proportion to that phase difference.
- LF (Loop Filter)
LF smooths the output pulse of the phase detector and the resulting DC component is the VCO input.
- VCO (Voltage Controlled Oscillator)
VCO is controlled by loop filter output. The output of the VCO is fed back to the phase frequency detector
input for comparison which in turn controls the VCO oscillating frequency to minimize the phase difference.
- FD (Frequency Divider)
FD divides too much different frequency that is oscillated from the VCO to compare it with reference signal
frequency.
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