DS_S1D2502A01 Datasheet, PDF (27/57 Pages) Samsung semiconductor – VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS

S1D2502A01
Preliminary
VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS
Registers
Frame Control
Registers — 0
(Row 15,
Column 00)
Table 11. Register Description (Continued)
Bits
HPOL
(Bit B)
VPOL
(Bit C)
FdeT
(Bit D)
Fde
(Bit E)
Bit F
Description
Polarity of horizontal fly back signal
If this bit is '1', HFLB's polarity is positive, and if '0', it is negative. In other
words, this bit is set to '1' if active high, and '0' if active low.
Polarity of vertical fly back signal
If this bit is '1', VFLB's polarity is positive, and if '0', it is negative. In other
words, this bit is set to '1' if active high, and '0' if active low.
Fade-in and fade-out time control
If this bit is '1', fade-in/fade-out time is 0.5sec. If not, it is 1sec.
Fade-in and fade-out enable
This feature is enabled when this bit is '1'. The effect where the display
goes from the center to the outside, or from the outside to the center in
units of font, is called fade-in/fade-out. Refer to fade-in/fade-out. You must
remember that fade-in/fade-out, like scrolling on/off, only occurs when OSD
enabled/disabled.
Reserved.
The purpose of bits 'HPOL', and 'VPOL' is to provide flexibility when using the S1D2502A01 IC. No matter which
polarity you choose for the input signal, the IC will handle them identically, so you can select active high or active
low according to your convenience.
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