DS_S1D2502A01 Datasheet, PDF (32/57 Pages) Samsung semiconductor – VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS

Preliminary
VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS
S1D2502A01
Registers
V-AMP Control
Registers - 11
(Row 15,
Column 14)
V-AMP Control
Registers - 12
(Row 15,
Column 15)
Tabel 4. Register Description (Continued)
Bits
CS2 — CS1
(bit1 — bit0)
Description
Cut-off offset current control
CS2 CS1
0
0
0
1
1
0
1
1
Cut-off Offset Current
0
50µA
100µA
150µA
POR
O
BPW2 — BPW1
(bit4 — bit3)
Generated clamp pulse width control
BPW2
0
0
1
1
BPW1
0
1
0
1
Width
0.33µs
0.66µs
1.00µs
1.33µs
POR
O
BLKP
(bit 5)
CLPP
(bit 6)
CLPS
(bit 7)
HS9 — HS7
(bit2 — bit 0)
To carry out this function, set the CLPS bit to " 0 "
Polarity of horizontral fly back signal
If this bit is ’0’, HFLB’s polarity is negative, and if ’1’, it is positive.
Polarity of clamp pulse signal
If this bit is ’0’, CLP’s polarity is positive, and if ’1’, it is negative.
This bit has meaning only if the CLPS bit is set to ’1’.
Clamp pulse generation enable
If this bit is ’0’, clamp signal is made using the HFLB signal, so there is
no need to supply the clamp signal.
and if ’1’ you must supply external clamp signal.
HS9 — HS7 bits select OSD raster color 3 to be half tone.
To carry out half tone function, set the HT bit to " 1 ".
HS9 HS8 HS7
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
OSD
G
R
B
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Raster
Color 3
Black
Blue
Red
Magenta
Green
Cyan
Yellow
White
POR
O
31