DS_S1D2502A01 Datasheet, PDF (48/57 Pages) Samsung semiconductor – VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS

Preliminary
VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS
S1D2502A01
• PLL of the S1D2502A01
PLL is composed of the phase detector, charge pump, VCO, and N-divider as 4 sub-blocks.
HFLB (Pin32)
Phase
Detector
CP_out
(Pin4)
Loop
Filter
# Composed of External Components
VCO_in
(Pin3)
Charge
Pump
VCO
VCO_out
Div_out
N-Divider
CP0 CP1 DOT0 DOT1 HF0 HF1 HF2
Figure 23. Block Diagram of the PLL Built in S1D2502A01
The following is the description of the input/output signals.
- HFLB (Input)
Horizontal flyback signal is refrence signal of the PLL built in S1D2502A01.
The HFLB signal's frequency range is 15 ~ 90kHz, so the PLL block must be a wide range PLL that can cover
HFLB's entire frequency range.
fHFLB
~2us
> 4.2V
< 0.4V
- VCO (Input)
Error signal that passes through an external loop filter is input into VCO.
Operation voltage range is 1-4V. You can raise immunity towards external noise by lowering VCO
sensitivity. You can do this by making it have the maximum operation voltage range possible in the 5V power
voltage.
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