UM_S3C2501X Datasheet, PDF (48/465 Pages) Samsung semiconductor – 32-BIT RISC MICROPROCESSOR

S3C2501X
PRODUCT OVERVIEW
Group
Ethernet
Controller1
(18)
Table 1-1. S3C2501X Signal Descriptions (Continue)
Pin Name
RX_CLK_1
RXD1[3:0]/
RXD_10M
RX_DV_1
LINK_10M
RX_ERR_1
Pin Type
1
I
4
I
1
I
1
I
Pad Type
phis
phis
phis
phisd
Description
Receive Clock/Receive Clock for 10M.
RX_CLK is a continuous clock signal. Its
frequency is 25 MHz for 100-Mbit/s operation,
and 2.5 MHz for 10-Mbit/s. RXD[3:0], RX_DV,
and RX_ERR are driven by the PHY off the
falling edge of RX_CLK, and sampled on the
rising edge of RX_CLK. To receive data, the
RXCLK_10 M clock comes from the 10Mbit/s
PHY.
Receive Data/Receive Data for 10M.
RXD is aligned on nibble boundaries. RXD[0]
corresponds to the first bit received on the
physical medium, which is the LSB of the byte
in one clock period and the fifth bit of that byte
in the next clock. RXD_10M is shared with
RXD[0] and it is a line for receiving data from
the 10-Mbit/s PHY.
Receive Data Valid.
PHY asserts RX_DV synchronously, holding it
active during the clock periods in which
RXD[3:0] contains valid data received. PHY
asserts RX_DV no later than the clock period
when it places the first nibble of the start
frame delimiter (SFD) on RXD[3:0]. If PHY
asserts RX_DV prior to the first nibble of the
SFD, then RXD[3:0] carries valid preamble
symbols. LINK_10M is shared with RX_DV
and used to convey the link status of the 10-
Mbit/s endec. The value is stored in a status
register.
Receive Error.
PHY asserts RX_ERR synchronously
whenever it detects a physical medium error
(e.g., a coding violation). PHY asserts
RX_ERR only when it asserts RX_DV.
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