UM_S3C2501X Datasheet, PDF (255/465 Pages) Samsung semiconductor – 32-BIT RISC MICROPROCESSOR

MEMORY CONTROLLER
S3C2501X
Table 5-19. Supported SDRAM Configuration of 32-bit External Bus
SDRAM
SDRAM # Banks
Technology Arrangement
16M-bit
2M x 8
1
2
1M x16
1
2
64M-bit
8M x 8
1
2
4M x 16
1
2
2M x 32
1
2
128M-bit
16M x 8
1
2
8M x 16
1
2
4M x 32
1
2
256M-bit
32M x 8
1
2
16M x 16
1
2
8M x 32
1
2
Address Size
Row
Col
11
9
11
8
12
9
12
8
11
8
12
10
12
9
12
8
13
10
13
9
13
8
Leaf Select
ADDR[14]
–
ADDR[13]
HADDR[21]
–
HADDR[21]
HADDR[22] HADDR[21]
HADDR[22] HADDR[21]
HADDR[22] HADDR[21]
HADDR[22] HADDR[21]
HADDR[22] HADDR[21]
HADDR[22] HADDR[21]
HADDR[22] HADDR[21]
HADDR[22] HADDR[21]
HADDR[22] HADDR[21]
NOTE: Banks: Number of external SDRAM memory bank used.
The controller supports up to two banks.
Leaf: Internal bank of SDRAM devices.
Total
Memory Size
(Byte)
8M
16 M
4M
8M
32 M
64 M
16 M
32 M
8M
16 M
64 M
128 M
32 M
64 M
16 M
32 M
128 M
256 M
64 M
128 M
32 M
64 M
5-40