UM_S3C2501X Datasheet, PDF (360/465 Pages) Samsung semiconductor – 32-BIT RISC MICROPROCESSOR

S3C2501X
31
B
S
GDMA CONTROLLER
RESERVED
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3
10
X
M
C
I D S T FS O R
N
E D D S BB D E
T
E
[0] Run enable (RE)
0 = Disable GDMA operation 1 = Enable GDMA operation
[3:1] Mode selection (MODE)
000 = Software mode (Memory to Memory)
001 = External Request mode (for external devices)
010 = HUART TX mode (HUART from memory) for GDMA 3, 4, 5
011 = HUART RX mode (HUART to memory) for GDMA 3, 4, 5
100 = DES IN mode (DES from memory)
101 = DES OUT mode (DES to memory)
110, 111 = Reserved
[4] Single/block mode (SB)
0 = One xGDMA_Req initiates a single GDMA operation
1 = One xGDMA_Req initiates a whole GDMA operation
[5] Four-data burst enable (FB)
0 = Disable 4-data burst mode
1 = Enable 4-data burst mode
[7:6] Transfer size (TS)
00 = Byte (8-bit)
10 = Word (32-bit)
01 = Half-word (16-bit)
11 = No use
[9:8] Source address direction (SD)
00 = Increase source address
01 = Decrease source address
10 = Do not change source address (fixed)
11 = Reserved
[11:10] Destination address direction (DD)
00 = Increase destination address
01 = Decrease destination address
10 = Do not change destination address (fixed)
11 = Reserved
[12] Interrupt enable (IE)
0 = Do not generate a interrupt when GDMA completes
1 = Generate a interrupt when GDMA completes successfully
[16:13] External GDMA ACK cycle count (XCNT)
0000 = 1 cycle
0001 = 2 cycle
0010 = 3 cycle
0100 = 5 cycle
0101 = 6 cycle
0110 = 7 cycle
1000 = 9 cycle
1001 = 10 cycle 1010 = 11 cycle
1100 = 13 cycle 1101 = 14 cycle 1110 = 15 cycle
0011 = 4 cycle
0111 = 8 cycle
1011 = 12 cycle
1111 = 16 cycle
[31] Busy status (BS)
0 = GDMA is idle
1 = GDMA is active
Figure 9-3. GDMA Control Register
9-11