UM_S3C2501X Datasheet, PDF (168/465 Pages) Samsung semiconductor – 32-BIT RISC MICROPROCESSOR

S3C2501X
3.26 FORMAT 7: LOAD/STORE WITH REGISTER OFFSET
INSTRUCTION SET
15 14 13 12 11 10 9
0 1 0 1 LB0
8
6
Ro
5
3
Rb
2
0
Rd
[2:0] Source/Destination Register
[5:3] Base Register
[8:6] Offset Register
[10] Byte/Word Flag
0 = Transfer word quantity
1 = Transfer byte quantity
[11] Load/Store Flag
0 = Store to memory
1 = Load from memory
Figure 3-36. Format 7
3.26.1 OPERATION
These instructions transfer byte or word values between registers and memory. Memory addresses are pre-
indexed using an offset register in the range 0-7. The THUMB assembler syntax is shown in Table 3-14.
Table 3-14. Summary of Format 7 Instructions
L B THUMB Assembler ARM Equivalent
Action
0 0 STR Rd, [Rb, Ro]
STR Rd, [Rb, Ro]
Pre-indexed word store:
Calculate the target address by adding together the
value in Rb and the value in Ro. Store the contents of
Rd at the address.
0 1 STRB Rd, [Rb, Ro]
STRB Rd, [Rb, Ro]
Pre-indexed byte store:
Calculate the target address by adding together the
value in Rb and the value in Ro. Store the byte value
in Rd at the resulting address.
1 0 LDR Rd, [Rb, Ro]
LDR Rd, [Rb, Ro]
Pre-indexed word load:
Calculate the source address by adding together the
value in Rb and the value in Ro. Load the contents of
the address into Rd.
1 1 LDRB Rd, [Rb, Ro]
LDRB Rd, [Rb, Ro]
Pre-indexed byte load:
Calculate the source address by adding together the
value in Rb and the value in Ro. Load the byte value
at the resulting address.
3-77