UM_S3C2501X Datasheet, PDF (38/465 Pages) Samsung semiconductor – 32-BIT RISC MICROPROCESSOR

S3C2501X
PRODUCT OVERVIEW
Group
System
Config
(20)
Table 1-1. S3C2501X Signal Descriptions (Continue)
Pin Name
CLKMOD [1:0]
Pin Type
2
I
CPU_FREQ [2:0] 3
I
BUS_FREQ [2:0] 3
I
nRESET
1
I
TMODE
1
I
BIG
1
I
Pad Type
Phic
phic
phic
phis
phicd
phicd
Description
The CLKMOD pin determines internal clock
scheme of S3C2501X. When CLKMOD is “00”,
the nfast clock mode is defined. In this mode,
the same clock is used as CPU clock and
system clock. When CLKMOD is “10”, the
sync mode is defined. In this mode, the system
clock is half frequency of the CPU clock.
When CLKMOD is "11", the async clock mode
is defined. In this mode, the CPU clock and
system clock can operate independently as
long as the CPU clock is faster than system
clock.
CPU Clock Frequency Selection.
System Bus Clock Frequency Selection.
Not Reset. NRESET is the global reset input
for the S3C2501X and nRESET must be held
to "low" for at least 64 clock cycles for digital
filtering.
Test Mode. The TMODE pin setting is
interpreted as follows:
0 = normal operating mode
1 = chip test mode.
BIG endian mode select pin
When this pin is set to “0”, the S3C2501X
operates in litte endian mode. When this pin is
set to “1”, the S3C2501X operates in big
endian mode.
1-13