UM_S3C2501X Datasheet, PDF (164/465 Pages) Samsung semiconductor – 32-BIT RISC MICROPROCESSOR

S3C2501X
3.24 FORMAT 5: HI-REGISTER OPERATIONS/BRANCH EXCHANGE
INSTRUCTION SET
15 14 13 12 11 10
000000
98
Op
76
H1 H2
5
3
Rs/Hs
2
0
Rd/Hd
[2:0] Destination Register
[5:3] Source Register
[6] Hi Operand Flag 2
[7] Hi Operand Flag 1
[9:8] Opcode
Figure 3-34. Format 5
3.24.1 OPERATION
There are four sets of instructions in this group. The first three allow ADD, CMP and MOV operations to be
performed between Lo and Hi registers, or a pair of Hi registers. The fourth, BX, allows a Branch to be performed
which may also be used to switch processor state. The THUMB assembler syntax is shown in Table 3-12.
NOTE
In this group only CMP (Op = 01) sets the CPSR condition codes.
The action of H1 = 0, H2 = 0 for Op = 00 (ADD), Op = 01 (CMP) and Op = 10 (MOV) is undefined, and should
not be used.
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