UM_S3C2501X Datasheet, PDF (301/465 Pages) Samsung semiconductor – 32-BIT RISC MICROPROCESSOR

ETHERNET CONTROLLER
S3C2501X
Buffer
Descriptor
Start Address
Register
+
BRXBDCNT+0
...
BRXBDCNT+1
...
buffer pointer #1
status
length
buffer pointer #2
status
length
...
BRXBDCNT+(N-1)
buffer pointer #N
status
length
Memory for Rx bufer descriptor
...
buffer #1
not u_...sed
buffer #2
not used
...
buffer #N
not used
Memory for frame
BRxBS of
BDMARXLEN
BRxBS of
BDMARXLEN
BRxBS of
BDMARXLEN
NOTE:
The BRxBS and BRxMFS of the BDMARXLEN register have to keep multiples of 16 in byte unit.
For long packet reception larger than 1518-byte, the BRxBS should be at least 4 bytes larger
than the BRxMFS or less than 1518-byte for the reception with a single or multiple buffer
descriptors, respectively.
Figure 7-4. Data Structure of the Receive Frame
7-12