UM_S3C2501X Datasheet, PDF (214/465 Pages) Samsung semiconductor – 32-BIT RISC MICROPROCESSOR

S3C2501X
SYSTEM CONFIGURATION
4.8.8 SYSTEM BUS PLL CONTROL REGISTER (SPLLCON)
If you want to use this register, you should set SPLLREN in SYSCFG[30] to “1”. This register doesn’t work with
SPLLREN set to “0”.
Register
SPLLCON
Address
0xF0000020
R/W
R/W
Description
System BUS PLL control register
Reset Value
0x0001037D
SPLLCON
Reserved
S
Reserved
P
M
Bit
[31:12]
[17:16]
[15:14]
[13:8]
[7:0]
Scaler
Pre divider
Main divider
Description
Initial State
0x0
0x1
0x0
0x3
0x7D
Output clock frequency is determined by following formula.
Fout = Fin × (M+8) / ((P+2) × (2^S))
If Fin = 10MHz, P = 3, M = 125 (0x7D), and S = 1, Fout is 133 MHz.
FCLK signal of ARM940T core is connected to Fout, 133MHz clock. But, BCLK signal of ARM940T and system
bus clock is connect to Fout / 2, 66 MHz clock.
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