UM_S3C2501X Datasheet, PDF (339/465 Pages) Samsung semiconductor – 32-BIT RISC MICROPROCESSOR

ETHERNET CONTROLLER
S3C2501X
7.5.5 TIMING PARAMETERS FOR MII TRANSACTIONS
The timing diagrams in this section conform to the guidelines described in the "Draft Supplement to ANSI/IEEE
Std. 802.3, Section 22.3, Signal Characteristics."
TX_CLK
TXD[3:0]
TX_EN
28ns MIN
Output Valid
4.9ns MIN
Figure 7-13. Timing Relationship of Transmission Signals at MII
RX_CLK
RXD[3:0]
RX_DV
Ts: 3ns
Th: 5ns
Input
Valid
Figure 7-14. Timing Relationship of Reception Signals at MII
MDC
MDIO
Ts: 15ns
Input Valid
Figure 7-15. MDIO Sourced by PHY
MDC
MDIO
Output Valid
Th: 13ns
Figure 7-16. MDIO Sourced by STA
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