UM_S3C2501X Datasheet, PDF (401/465 Pages) Samsung semiconductor – 32-BIT RISC MICROPROCESSOR

SERIAL I/O (HIGH-SPEED UART)
S3C2501X
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 8 7 6 5 4 3 2 1 0
RESH
TCF F
S HE E
R ON N
T
R
RD R T RTRT
I W S P LASS R T
T T F F F F F F R L T M OUCB M M
SR T T RREE
B D OBSR O O
L L SSNN
PDE
DD
TT
BL
EE
[16] Transmit FIFO Enable (TFEN)
0 = Disable Transmit FIFO
1 = Enable Transmit FIFO
[17] Receive FIFO Enable (RFEN)
0 = Disable Receive FIFO
1 = Enable Receive FIFO
[18] Tranmit FIFO Reset (TFRST)
0 = Normal operation
1 = Reset Transmit FIFO
[19] Receive FIFO Reset (RFRST)
0 = Normal operation
1 = Reset Receive FIFO
[21:20] Transmit FIFO Trigger Level (TFTL)
00 = 30/32 byte data
01 = 24/32 byte data
10 = 16/32 byte data
11 = 8/32 byte data (empty Tx data / TxFIFO depth)
[23:22] Receive FIFO Trigger Level (RFTL)
00 = 1/32 byte data
01 = 8/32 byte data
10 = 18/32 byte data
11 = 28/32 byte data (valid Rx data / RxFIFO depth)
[24] Data Terminal Ready to pin (DTR)
0 = HUnDTR goes high level
1 = HUnDTR goes low level
[25] Request To Send to pin (RTS)
0 = HUnRTS goes high level
1 = HUnRTS goes low level
[27:26] Reserved (This bit should be cleared)
[28] Hardware Flow Control Enable (HFEN)
0 = Disable Hardware Flow Control
1 = Enable Hardware Flow Control
[29] Software Flow Control Enable (SFEN)
0 = Disable Software Flow Control
1 = Enable Software Flow Control
[30] Echo Mode (ECHO)
0 = Normal
1 = ECHO mode
[31] RTS/RTR selection (RTS/RTR)
0 = RTS
1 = RTR
Figure 11-2. High-Speed UART Control Register (Continued)
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