M393B1K73DH0 Datasheet, PDF (43/56 Pages) Samsung semiconductor – 240pin Registered DIMM

Registered DIMM
datasheet
Rev. 1.3
DDR3 SDRAM
[ Table 20 ] Timing Parameters by Speed Bins for DDR3-800 to DDR3-1333
Speed
Parameter
Power Down Timing
Exit Power Down with DLL on to any valid command;Exit Pre-
charge Power Down with DLL
frozen to commands not requiring a locked DLL
Exit Precharge Power Down with DLL frozen to commands re-
quiring a locked DLL
CKE minimum pulse width
Command pass disable delay
Power Down Entry to Exit Timing
Timing of ACT command to Power Down entry
Timing of PRE command to Power Down entry
Timing of RD/RDA command to Power Down entry
Timing of WR command to Power Down entry
(BL8OTF, BL8MRS, BC4OTF)
Timing of WRA command to Power Down entry
(BL8OTF, BL8MRS, BC4OTF)
Timing of WR command to Power Down entry
(BC4MRS)
Timing of WRA command to Power Down entry
(BC4MRS)
Timing of REF command to Power Down entry
Timing of MRS command to Power Down entry
ODT Timing
ODT high time without write command or with write command
and BC4
ODT high time with Write command and BL8
Asynchronous RTT turn-on delay (Power-Down with DLL fro-
zen)
Asynchronous RTT turn-off delay (Power-Down with DLL fro-
zen)
RTT turn-on
RTT_NOM and RTT_WR turn-off time from ODTLoff reference
RTT dynamic change skew
Write Leveling Timing
First DQS/DQS rising edge after write leveling mode is pro-
grammed
DQS/DQS delay after write leveling mode is programmed
Write leveling setup time from rising CK, CK crossing to rising
DQS, DQS crossing
Write leveling hold time from rising DQS, DQS crossing to rising
CK, CK crossing
Write leveling output delay
Write leveling output error
Symbol
DDR3-800
MIN
MAX
tXP
tXPDLL
tCKE
tCPDED
tPD
tACTPDEN
tPRPDEN
tRDPDEN
tWRPDEN
max
(3nCK,
7.5ns)
max
(10nCK,
24ns)
max
(3nCK,
7.5ns)
1
tCKE(min)
1
1
RL + 4 +1
WL + 4
+(tWR/
tCK(avg))
tWRAPDEN WL+4+WR +1
tWRPDEN
tWRAPDEN
tREFPDEN
tMRSPDEN
WL + 2
+(tWR/
tCK(avg))
WL +2 +WR
+1
1
tMOD(min)
-
-
-
-
9*tREFI
-
-
-
-
-
-
-
-
-
ODTH4
4
-
ODTH8
6
-
tAONPD
2
8.5
tAOFPD
2
8.5
tAON
tAOF
tADC
-400
400
0.3
0.7
0.3
0.7
tWLMRD
40
-
tWLDQSEN
25
-
tWLS
325
-
tWLH
325
-
tWLO
0
9
tWLOE
0
2
DDR3-1066
MIN
MAX
max
(3nCK,
7.5ns)
max
(10nCK,
24ns)
max
(3nCK,
5.625ns)
1
tCKE(min)
1
1
RL + 4 +1
WL + 4
+(tWR/
tCK(avg))
WL+4+WR+1
WL + 2
+(tWR/
tCK(avg))
WL +2 +WR
+1
1
tMOD(min)
-
-
-
-
9*tREFI
-
-
-
-
-
-
-
-
-
4
-
6
-
2
8.5
2
8.5
-300
300
0.3
0.7
0.3
0.7
40
-
25
-
245
-
245
-
0
9
0
2
DDR3-1333
MIN
MAX
max
(3nCK,6ns)
max
(10nCK,
24ns)
max
(3nCK,
5.625ns)
1
tCKE(min)
1
1
RL + 4 +1
WL + 4
+(tWR/
tCK(avg))
WL+4+WR+1
WL + 2
+(tWR/
tCK(avg))
WL +2 +WR
+1
1
tMOD(min)
-
-
-
-
9*tREFI
-
-
-
-
-
-
-
-
-
4
-
6
-
2
8.5
2
8.5
-250
250
0.3
0.7
0.3
0.7
40
-
25
-
195
-
195
-
0
9
0
2
Units
nCK
tCK
nCK
nCK
nCK
nCK
nCK
nCK
nCK
nCK
ns
ns
ps
tCK(avg)
tCK(avg)
tCK
tCK
ps
ps
ns
ns
NOTE
2
15
20
20
9
10
9
10
20,21
7,f
8,f
f
3
3
- 43 -