M393B1K73DH0 Datasheet, PDF (12/56 Pages) Samsung semiconductor – 240pin Registered DIMM

Registered DIMM
datasheet
10.2 4GB,512Mx72 Module (Populated as 2 ranks of x8 DDR3 SDRAMs)
Rev. 1.3
DDR3 SDRAM
DQS8
DQS8
DM8/DQS17
DQS17
CB[7:0]
DQS
DQS
TDQS
TDQS
D8
DQ[7:0]
ZQ
DQS
DQS
TDQS
TDQS
DQ[7:0]
ZQ
D17
DQS4
DQS4
DM4/DQS13
DQS13
DQ[39:32]
DQS
DQS
TDQS
TDQS
D4
DQ[7:0]
ZQ
DQS
DQS
TDQS
TDQS
DQ[7:0]
ZQ
D13
DQS3
DQS3
DM3/DQS12
DQS12
DQ[31:24]
DQS
DQS
TDQS
TDQS
D3
DQ[7:0]
ZQ
DQS
DQS
TDQS
TDQS
DQ[7:0]
ZQ
D12
DQS5
DQS5
DM5/DQS14
DQS14
DQ[47:40]
DQS
DQS
TDQS
TDQS
D5
DQ[7:0]
ZQ
DQS
DQS
TDQS
TDQS
DQ[7:0]
ZQ
D14
DQS2
DQS2
DM2/DQS11
DQS11
DQ[23:16]
DQS
DQS
TDQS
TDQS
D2
DQ[7:0]
ZQ
DQS
DQS
TDQS
TDQS
DQ[7:0]
ZQ
D11
DQS6
DQS6
DM6/DQS15
DQS15
DQ[55:48]
DQS
DQS
TDQS
TDQS
D6
DQ[7:0]
ZQ
DQS
DQS
TDQS
TDQS
DQ[7:0]
ZQ
D15
DQS1
DQS1
DM1/DQS10
DQS10
DQ[15:8]
DQS
DQS
TDQS
TDQS
D1
DQ[7:0]
ZQ
DQS
DQS
TDQS
TDQS
DQ[7:0]
ZQ
D10
DQS7
DQS7
DM7/DQS16
DQS16
DQ[63:56]
DQS
DQS
TDQS
TDQS
D7
DQ[7:0]
ZQ
DQS
DQS
TDQS
TDQS
DQ[7:0]
ZQ
D16
DQS0
DQS0
DM0/DQS9
DQS9
DQ[7:0]
DQS
DQS
TDQS
TDQS
D0
DQ[7:0]
ZQ
Vtt
DQS
DQS
TDQS
TDQS
D9
DQ[7:0]
ZQ
Vtt
S0*
S1*
BA[N:0]
A[N:0]
V_DDSPD
V_DD
V_TT
V_REFCA
V_REFDQ
V_SS
Serial PD
D0 - D17
SCL
EVENT
Thermal sensor with SPD
EVENT
A0 A1 A2
D0 - D17
D0 - D17
D0 - D17
SA0 SA1 SA2
SDA
RAS
CAS
WE
CKE0
CKE1
ODT0
ODT1
NOTE :
1. Unless otherwise noted, resistor values are 15Ω ± 5%.
2. RS0 and RS1 alternate between the back and front sides of the DIMM.
3. ZQ resistors are 240Ω ± 1% . For all other resistor values refer to the appropriate
wiring diagram.
4. See the wiring diagrams for all resistors associated with the command, address
and control bus.
CK0
CK0
PAR_IN
RESET**
1:2
R
E
G
I
S
T
E
R
QERR
RST
RS0A-> CS0 : SDRAMs D[3:0], D8
RS0B-> CS0 : SDRAMs D[7:4]
RS1A-> CS1 : SDRAMs D[12:9], D17
RS1B-> CS1 : SDRAMs D[16:13]
RBA[N:0]A -> BA[N:0] : SDRAMs D[3:0], D[12:8], D17
RBA[N:0]B -> BA[N:0] : SDRAMs D[7:4], D[16:13]
RA[N:0]A -> A[N:0] : SDRAMs D[3:0], D[12:8], D17
RA[N:0]B -> A[N:0] : SDRAMs D[7:4, D[16:13]]
RRASA -> RAS : SDRAMs D[3:0], D[12:8], D17
RRASB -> RAS : SDRAMs D[7:4], D[16:13]
RCASA -> CAS : SDRAMs D[3:0], D[12:8], D17
RCASB -> CAS : SDRAMs D[7:4], D[16:13]
RWEA -> WE : SDRAMs D[3:0], D[12:8], D17
RWEB -> WE : SDRAMs D[7:4], D[16:13]
RCKE0A -> CKE0 : SDRAMs D[3:0], D8
RCKE0B -> CKE0 : SDRAMs D[7:4]
RCKE1A -> CKE1 : SDRAMs D[12:9], D17
RCKE1B -> CKE1 : SDRAMs D[16:13]
RODT0A -> ODT0 : SDRAMs D[3:0], D8
RODT0B -> ODT0 : SDRAMs D[7:4]
RODT1A -> ODT1 : SDRAMs D[12:9], D17
RODT1A -> ODT1 : SDRAMs D[16:13]
PCK0A -> CK : SDRAMs D[3:0], D8
PCK0B -> CK : SDRAMs D[7:4]
PCK1A -> CK : SDRAMs D[12:9], D17
PCK1B -> CK : SDRAMs D[16:13]
PCK0A -> CK : SDRAMs D[3:0], D8
PCK0B -> CK : SDRAMs D[7:4]
PCK1A -> CK : SDRAMs D[12:9], D17
PCK1B -> CK : SDRAMs D[16:13]
Err_out
RST** : SDRAMs D[8:0]
*S[3:2], CKE1, ODT1, CK1 and CK1 are NC
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