M393B1K73DH0 Datasheet, PDF (10/56 Pages) Samsung semiconductor – 240pin Registered DIMM

Registered DIMM
datasheet
Rev. 1.3
DDR3 SDRAM
9. Registering Clock Driver Specification
9.1 Timing & Capacitance values
Symbol
Parameter
Conditions
fclock
t_CH/t_CL
Input Clock Frequency
Pulse duration, CK, CK HIGH or LOW
t_ACT
Inputs active time4 before RESET is taken HIGH
t_SU
Setup time
t_H
Hold time
t_PDM
t_DIS
t_EN
C_IN(DATA)
C_IN(CLOCK)
C_IN(RST)
Propagation delay, single-bit switching
output disable time(1/2-Clock pre-launch)
output disable time(3/4-Clock pre-launch)
output enable time(1/2-Clock pre-launch)
output enable time(3/4-Clock pre-launch)
Data Input Capacitance
Data Input Capacitance
Reset Input Capacitance
application frequency
DCKE0/1 = LOW and
DCS0/1 = HIGH
Input valid before CK/CK
Input to remain Valid after CK/
CK
CK/CK to output
CK/CK to output float
CK/CK to output driving
T_C = TBD
V_DD = 1.5 ± 0.075V
Min
Max
300
670
0.4
-
8
-
100
-
175
-
0.65
1.0
0.5
-
0.25
-
-
0.5
-
0.25
1.5
2.5
2
3
-
3
Units Notes
MHz
t_CK
t_CK
ps
ns
t_CK
t_CK
pF
9.2 Clock driver Characteristics
Symbol
Parameter
Conditions
t_jit (cc)
t_STAB
t_fdyn
t_CKsk
t_jit(per)
t_jit(hper)
t_Qsk1
t_Qsk1
t_dynoff
Cycle-to-cycle period jitter
Stabilization time
Dynamic phase offset
Clock Output skew
Yn Clock Period jitter
Half period jitter
Qn Output to clock tolerance (Standard 1/2 -Clock
Pre-Launch)
Output clock tolerance (3/4 Clock Pre-Launch)
Maximum re-driven dynamic clock off-set
Output Inversion enabled
OUtput Inversion disabled
Output Inversion enabled
OUtput Inversion disabled
T_C = TBD
V_DD = 1.5 ± 0.075V
Min
Max
0
40
-
6
-50
50
50
-40
40
-50
50
-100
200
-100
300
-100
200
-100
300
-80
80
Units Notes
ps
us
ps
ps
ps
ps
ps
ps
ps
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