M393T3253FG Datasheet, PDF (4/18 Pages) Samsung semiconductor – DDR2 Registered SDRAM MODULE 240pin Registered Module based on 256Mb F-die 72-bit ECC

256MB, 512MB Registered DIMMs
DDR2 SDRAM
Input/Output Functional Description
Symbol
CK0
CK0
CKE0~CKE1
S0~S1
ODT0~ODT1
RAS, CAS, WE
V_REF
V_DDQ
BA0~BA1
A0~A9,A10/AP
A11~A12
DQ0~63,
CB0~CB7
DM0~DM8
V_DD, V_SS
DQS0~DQS17
DQS0~DQS17
SA0~SA2
SDA
SCL
V_DDSPD
RESET
Par_In
Err_Out
TEST
Type
Input
Input
Input
Input
Input
Input
Supply
Supply
Input
Input
Function
Positive line of the differential pair of system clock inputs that drives input to the on-DIMM PLL.
Negative line of the differential pair of system clock inputs that drives the input to the on-DIMM PLL.
Activates the SDRAM CK signal when high and deactivates the CK signal when low. By deactivating the clocks, CKE low
initiates the Power Down mode, or the Self Refresh mode.
Enables the associated SDRAM command decoder when low and disables decoder when high. When decoder is dis-
abled, new commands are ignored but previous operations continue.
These input signals also disable all outputs (except CKE and ODT) of the register(s) on the DIMM when both inputs are
high.
I/O bus impedance control signals.
When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the operation to be executed by the
SDRAM.
Reference voltage for SSTL_18 inputs
Isolated power supply for the DDR SDRAM output buffers to provide improved noise immunity
Selects which SDRAM bank of four is activated.
During a Bank Activate command cycle, Address defines the row address.
During a Read or Write command cycle, Address defines the column address. In addition to the column address, AP is
used to invoke autoprecharge operation at the end of the burst read or write cycle. If AP is high, autoprecharge is
selected and BA0, BA1 defines the bank to be precharged. If AP is low, autoprecharge is disabled. During a Precharge
command cycle, AP is used in conjunction with BA0, BA1 to control which bank(s) to precharge. If AP is high, all banks
will be precharged regardless of the state of BA0 or BA1. If AP is low, BA0 and BA1 are used to define which bank to pre-
charge.
In/Out _{Data and Check Bit Input/Output pins}
Input
Supply
In/Out
In/Out
Input
In/Out
Input
Supply
Input
Input
Input
In/Out
Masks write data when high, issued concurrently with input data. Both DM and DQ have a write latency of one clock once
the write command is registered into the SDRAM.
Power and ground for the DDR SDRAM input buffers and core logic
Positive line of the differential data strobe for input and output data.
Negative line of the differential data strobe for input and output data.
These signals are tied at the system planar to either V_SS or V_DDSPD to configure the serial SPD EEPROM address range.
This bidirectional pin is used to transfer data into or out of the SPD EEPROM. A resistor must be connected from the SDA
bus line to V_DDSPD to act as a pullup.
This signal is used to clock data into and out of the SPD EEPROM. A resistor may be connected from the SCL bus time
to V_DDSPD to act as a pullup.
Serial EEPROM positive power supply (wired to a separate power pin at the connector which supports from 1.7 Volt to
3.6 Volt operation).
The RESET pin is connected to the RST pin on the register and to the OE pin on the PLL. When low, all register outputs
will be driven low and the PLL clocks to the DRAMs and register(s) will be set to low level (The PLL will remain synchro-
nized with the input clock )
Parity bit for the Address and Control bus. ( “1 “ : Odd, “0 “ : Even)
Parity error found in the Address and Control bus
Used by memory bus analysis tools (unused on memory DIMMs)
Rev. 1.3 Aug. 2005