M393T3253FG Datasheet, PDF (17/18 Pages) Samsung semiconductor – DDR2 Registered SDRAM MODULE 240pin Registered Module based on 256Mb F-die 72-bit ECC

256MB, 512MB Registered DIMMs
240 Pin DDR2 Registered DIMM Clock Topology
CK0
CK0
0ns (nominal)
PLL
OUT1
120 ohms
IN
120 ohms
OUTN
C
Feedback In
Feedback Out
DDR2 SDRAM
DDR2 SDRAM
120 ohms
DDR2 SDRAM
Reg.A
C
Reg.B
120 ohms
Note:
1. The clock delay from the input of the PLL clock to the input of any DDR2 SDRAM or register will be set to 0ns (nominal).
2. Input, output, and feedback clock lines are terminated from line to line as shown, and not from line to ground.
3. Only one PLL output is shown per output type. Any additional PLL outputs will be wired in a similar manner.
4. Termination resistors for the PLL feedback path clocks are located as close to the input pin of the PLL as possible.
Rev. 1.3 Aug. 2005