M393T3253FG Datasheet, PDF (2/18 Pages) Samsung semiconductor – DDR2 Registered SDRAM MODULE 240pin Registered Module based on 256Mb F-die 72-bit ECC

256MB, 512MB Registered DIMMs
DDR2 SDRAM
DDR2 Registered DIMM Ordering Information
Part Number
M393T3253FG(Z)3-CD5/CC
M393T3253FG(Z)0-CD5/CC
M393T3253FZA-CE6/D5/CC
M393T6453FG(Z)3-CD5/CC
M393T6453FG(Z)0-CD5/CC
M393T6453FZA-CE6/D5/CC
M393T6450FG(Z)3-CD5/CC
M393T6450FG(Z)0-CD5/CC
M393T6450FZA-CE6/D5/CC
Density
256MB
256MB
256MB
512MB
512MB
512MB
512MB
512MB
512MB
Organization
32Mx72
32Mx72
32Mx72
64Mx72
64Mx72
64Mx72
64Mx72
64Mx72
64Mx72
Component Composition
32Mx8(K4T56083QF)*9EA
32Mx8(K4T56083QF)*9EA
32Mx8(K4T56083QF)*9EA
32Mx8(K4T56083QF)*18EA
32Mx8(K4T56083QF)*18EA
32Mx8(K4T56083QF)*18EA
64Mx4(K4T56043QF)*18EA
64Mx4(K4T56043QF)*18EA
64Mx4(K4T56043QF)*18EA
Note: “Z” of Part number(11th digit) stand for Lead-free products.
Note: “3” of Part number(12th digit) stand for Dummy Pad PCB products.
Note: "A" of Part number(12th digit) stand for Parity Register products.
Number of Rank
1
1
1
2
2
2
1
1
1
Parity Register
X
X
O
X
X
O
X
X
O
Height
30mm
30mm
30mm
30mm
30mm
30mm
30mm
30mm
30mm
Features
• Performance range
E6 (DDR2-667)
Speed@CL3
400
Speed@CL4
533
Speed@CL5
667
CL-tRCD-tRP
5-5-5
D5 (DDR2-533)
400
533
-
4-4-4
CC (DDR2-400)
400
400
-
3-3-3
Unit
Mbps
Mbps
Mbps
CK
• JEDEC standard 1.8V ± 0.1V Power Supply
• V_DDQ = 1.8V ± 0.1V
• 200 MHz f_CK for 400Mb/sec/pin, 267MHz f_CK for 533Mb/sec/pin, 333MHz f_CK for 667Mb/sec/pin
• 4 Banks
• Posted CAS
• Programmable CAS Latency: 3, 4, 5
• Programmable Additive Latency: 0, 1 , 2 , 3 and 4
• Write Latency(WL) = Read Latency(RL) -1
• Burst Length: 4 , 8(Interleave/nibble sequential)
• Programmable Sequential / Interleave Burst Mode
• Bi-directional Differential Data-Strobe (Single-ended data-strobe is an optional feature)
• Off-Chip Driver(OCD) Impedance Adjustment
• On Die Termination
• Average Refresh Period 7.8us at lower than T_CASE 85°C, 3.9us at 85°C < T_CASE < 95°C
• Serial presence detect with EEPROM
• DDR2 SDRAM Package: 60ball FBGA - 64Mx4/32Mx8
• All of Lead-free products are compliant for RoHS
Note : For detailed DDR2 SDRAM operation, please refer to Samsung’s Device operation & Timing diagram.
Address Configuration
Organization
64Mx4(256Mb) based Module
32Mx8(256Mb) based Module
Row Address
A0-A12
A0-A12
Column Address
A0-A9,A11
A0-A9
Bank Address
BA0-BA1
BA0-BA1
Auto Precharge
A10
A10
Rev. 1.3 Aug. 2005