M393T3253FG Datasheet, PDF (14/18 Pages) Samsung semiconductor – DDR2 Registered SDRAM MODULE 240pin Registered Module based on 256Mb F-die 72-bit ECC

256MB, 512MB Registered DIMMs
DDR2 SDRAM
Parameter
Symbol
DQS input low pulse width
tDQSL
DQS falling edge to CK setup time
tDSS
DQS falling edge hold time from CK
tDSH
Mode register set command cycle time
tMRD
Write postamble
tWPST
Write preamble
tWPRE
Address and control input hold time
tIH
Address and control input setup time
tIS
Read preamble
tRPRE
Read postamble
tRPST
Active to active command period for 1KB page
size products
tRRD
Active to active command period for 2KB page
size products
tRRD
Four Activate Window for 1KB page size
products
tFAW
Four Activate Window for 2KB page size
products
tFAW
CAS to CAS command delay
tCCD
Write recovery time
tWR
Auto precharge write recovery + precharge time tDAL
Internal write to read command delay
tWTR
Internal read to precharge command delay
tRTP
Exit self refresh to a non-read command
tXSNR
Exit self refresh to a read command
tXSRD
Exit precharge power down to any non-read
command
tXP
Exit active power down to read command
tXARD
Exit active power down to read command
(Slow exit, Lower power)
CKE minimum pulse width
(high and low pulse width)
tXARDS
tCKE
ODT turn-on delay
tAOND
ODT turn-on
tAON
ODT turn-on(Power-Down mode)
tAONPD
ODT turn-off delay
tAOFD
ODT turn-off
tAOF
ODT turn-off (Power-Down mode)
ODT to power down entry latency
ODT power down exit latency
OCD drive mode output delay
Minimum time clocks remains ON after CKE
asynchronously drops LOW
tAOFPD
tANPD
tAXPD
tOIT
tDelay
DDR2-667
min
max
0.35
x
0.2
x
0.2
x
2
x
0.4
0.6
0.35
x
275
x
200
x
0.9
1.1
0.4
0.6
7.5
x
DDR2-533
min
max
0.35
x
0.2
x
0.2
x
2
x
0.4
0.6
0.35
x
375
x
250
x
0.9
1.1
0.4
0.6
7.5
x
DDR2-400
min
max
0.35
x
0.2
x
0.2
x
2
x
0.4
0.6
0.35
x
475
x
350
x
0.9
1.1
0.4
0.6
7.5
x
Units Notes
tCK
tCK
tCK
tCK
tCK
tCK
ps
ps
tCK
tCK
ns
10
x
10
x
10
x
ns
37.5
37.5
37.5
ns
50
50
50
ns
2
2
2
tCK
15
x
15
x
15
x
ns
tWR+tRP
x
tWR+tRP
x
tWR+tRP
x
tCK
7.5
x
7.5
x
10
x
ns
7.5
7.5
7.5
ns
tRFC + 10
tRFC + 10
tRFC + 10
ns
200
200
200
tCK
2
x
2
x
2
x
tCK
2
x
2
x
2
x
tCK
6 - AL
6 - AL
6 - AL
tCK
3
3
3
tCK
2
2
2
2
2
2
tCK
tAC(min) tAC(max)+0.7 tAC(min) tAC(max)+1 tAC(min) tAC(max)+1 ns
tAC(min)+2
2tCK+tAC(ma
x)+1
tAC(min)+2
2tCK+tAC(ma
x)+1
tAC(min)+2
2tCK+tAC
(max)+1
ns
2.5
2.5
2.5
2.5
2.5
2.5
tCK
tAC(min)
tAC(max)+
0.6
tAC(min)
tAC(max)+ 0.6 tAC(min) tAC(max)+ 0.6 ns
tAC(min)+2
2.5tCK+tAC(
max)+1
tAC(min)+2
2.5tCK+
tAC(max)+1
tAC(min)+2
2.5tCK+
tAC(max)+1
ns
3
3
3
tCK
8
8
8
tCK
0
12
0
12
0
12
ns
tIS+tCK +tIH
tIS+tCK +tIH
tIS+tCK +tIH
ns
Rev. 1.3 Aug. 2005