M393T3253FG Datasheet, PDF (10/18 Pages) Samsung semiconductor – DDR2 Registered SDRAM MODULE 240pin Registered Module based on 256Mb F-die 72-bit ECC

256MB, 512MB Registered DIMMs
DDR2 SDRAM
IDD Specification Parameters Definition
(IDD values are for full operating range of Voltage and Temperature)
Symbol
IDD0
IDD1
IDD2P
IDD2Q
IDD2N
IDD3P
IDD3N
IDD4W
IDD4R
IDD5B
IDD6
IDD7
Proposed Conditions
Operating one bank active-precharge current;
tCK ₌ tCK(IDD), tRC ₌ tRC(IDD), tRAS ₌ tRASmin(IDD); _{CKE is HIGH, CS\ is HIGH between valid commands;}
Address bus inputs are SWITCHING; Data bus inputs are SWITCHING
Operating one bank active-read-precharge current;
IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; ^tCK = ^{tCK(IDD), tRC} = ^tRC (IDD), ^tRAS = ^{tRASmin(IDD), tRCD} =
tRCD(IDD); _{CKE is HIGH, CS\ is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern}
is same as IDD4W
Precharge power-down current;
All banks idle; tCK = ^tCK(IDD); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are
FLOATING
Precharge quiet standby current;
All banks idle; ^tCK = ^tCK(IDD); CKE is HIGH, CS\ is HIGH; Other control and address bus inputs are STABLE; Data
bus inputs are FLOATING
Precharge standby current;
All banks idle; ^tCK = ^tCK(IDD); CKE is HIGH, CS\ is HIGH; Other control and address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
Active power-down current;
All banks open; ^tCK = ^tCK(IDD); CKE is LOW; Other control and address bus
inputs are STABLE; Data bus inputs are FLOATING
Fast PDN Exit MRS(12) = 0mA
Slow PDN Exit MRS(12) = 1mA
Active standby current;
All banks open; ^tCK = ^{tCK(IDD), tRAS} = ^{tRASmax(IDD), tRP} = ^tRP(IDD); CKE is HIGH, CS\ is HIGH between valid
commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING
Operating burst write current;
All banks open, Continuous burst writes; BL = 4, CL = CL(IDD), AL = 0; ^tCK = ^{tCK(IDD), tRAS} = ^{tRASmax(IDD), tRP}
= ^tRP(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus
inputs are SWITCHING
Operating burst read current;
All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; ^tCK = ^{tCK(IDD), tRAS} = ^tRAS-
max(IDD), ^tRP = ^tRP(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Address bus inputs are SWITCH-
ING; Data pattern is same as IDD4W
Burst auto refresh current;
tCK ₌ tCK(IDD); _{Refresh command at every} tRFC(IDD) _{interval; CKE is HIGH, CS\ is HIGH between valid commands;}
Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING
Self refresh current;
CK and CK\ at 0V; CKE ≤ 0.2V; Other control and address bus inputs are
FLOATING; Data bus inputs are FLOATING
Normal
Low Power
Operating bank interleave read current;
All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = ^{tRCD(IDD)-1*tCK(IDD); tCK} = ^{tCK(IDD), tRC} =
tRC(IDD), tRRD ₌ tRRD(IDD), tFAW ₌ tFAW(IDD), tRCD _{= 1*tCK(IDD); CKE is HIGH, CS\ is HIGH between valid}
commands; Address bus inputs are STABLE during DESELECTs; Data pattern is same as IDD4R; Refer to the follow-
ing page for detailed timing conditions
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Notes
Rev. 1.3 Aug. 2005