K4R271669B Datasheet, PDF (17/20 Pages) Samsung semiconductor – 256K x 16/18 bit x 32s banks Direct RDRAMTM

K4R271669B/K4R441869B
Direct RDRAM^™
Timing Parameters
Parameter
t_RC
t_RAS
t_RP
t_PP
t_RR
t_RCD
t_CAC
t_CWD
t_CC
t_PACKET
t_RTR
t_OFFP
t_RDP
t_RTP
Table 13: Timing Parameter Summary
Description
Min Min Min
-45 -45 -53.3 Max Units
-800 -711 -600
Row Cycle time of RDRAM banks -the interval between ROWA packets with 28 28 28 -
ACT commands to the same bank.
t_CYCLE
RAS-asserted time of RDRAM bank - the interval between ROWA packet 20
with ACT command and next ROWR packet with PRER^a command to the
same bank.
20 20
64µs^b t_CYCLE
Row Precharge time of RDRAM banks - the interval between ROWR packet 8
8
8
-
with PRER^a command and next ROWA packet with ACT command to the
same bank.
t_CYCLE
Precharge-to-precharge time of RDRAM device - the interval between succes- 8
8
8
-
sive ROWR packets with PRER^a commands to any banks of the same device.
t_CYCLE
RAS-to-RAS time of RDRAM device - the interval between successive
ROWA packets with ACT commands to any banks of the same device.
8
8
8
-
t_CYCLE
RAS-to-CAS Delay - the interval from ROWA packet with ACT command to 9
7
7
-
COLC packet with RD or WR command). Note - the RAS-to-CAS delay seen
by the RDRAM core (t_RCD-C) is equal to t_RCD-C = 1 + t_RCD because of differ-
ences in the row and column paths through the RDRAM interface.
t_CYCLE
CAS Access delay - the interval from RD command to Q read data. The equa- 8
8
8
12
t_CYCLE
tion for t_CAC is given in the TPARM register in Figure 40.
CAS Write Delay (interval from WR command to D write data.
6
6
6
6
t_CYCLE
CAS-to-CAS time of RDRAM bank - the interval between successive COLC 4
4
4
-
commands).
t_CYCLE
Length of ROWA, ROWR, COLC, COLM or COLX packet.
4
4
4
4
t_CYCLE
Interval from COLC packet with WR command to COLC packet which causes 8
8
8
-
retire, and to COLM packet with bytemask.
t_CYCLE
The interval (offset) from COLC packet with RDA command, or from COLC 4
4
4
4
t_CYCLE
packet with retire command (after WRA automatic precharge), or from COLC
packet with PREC command, or from COLX packet with PREX command to
the equivalent ROWR packet with PRER. The equation for t_OFFP is given in
the TPARM register in Figure 40.
Interval from last COLC packet with RD command to ROWR packet with 4
4
4
-
PRER.
t_CYCLE
Interval from last COLC packet with automatic retire command to ROWR 4
4
4
-
packet with PRER.
t_CYCLE
Figure(s)
Figure 16
Figure 17
Figure 16
Figure 17
Figure 16
Figure 17
Figure 13
Figure 14
Figure 16
Figure 17
Figure 5
Figure 40
Figure 5
Figure 16
Figure 17
Figure 3
Figure 18
Figure 15
Figure 40
Figure 16
Figure 17
a. Or equivalent PREC or PREX command. See Figure 15.
b. This is a constraint imposed by the core, and is therefore in units of µs rather than t_CYCLE.
Page 15
Version 1.11 Oct. 2000