K4R271669B Datasheet, PDF (15/20 Pages) Samsung semiconductor – 256K x 16/18 bit x 32s banks Direct RDRAMTM

K4R271669B/K4R441869B
Direct RDRAM^™
Symbol
t_REF
t_BURST
t_CCTRL
t_TEMP
t_TCEN
t_TCAL
t_TCQUIET
t_PAUSE
Table 11: Timing Conditions
Parameter
Refresh interval
Interval after PDN or NAP (with self-refresh) exit in which all
banks of the RDRAM must be refreshed at least once.
Current control interval
Temperature control interval
TCE command to TCAL command
TCAL command to quiet window
Quiet window (no read data)
RDRAM delay (no RSL operations allowed)
Min
34 t_CYCLE
150
2
140
Max
32
200
100ms
100
-
2
-
200.0
Unit
ms
µs
ms/t_CYCLE
ms
t_CYCLE
t_CYCLE
t_CYCLE
µs
Figure(s)
Figure 51
Figure 52
Figure 53
Figure 54
Figure 54
Figure 54
Figure 54
page 38
a. MSE/MS are fields of the SKIP register. For this combination (skip override) the tDCW parameter range is effectively 0.0 to 0.0.
b. This parameter also applies to a -800 or -711 part when operated with t_CYCLE=3.33ns.
c. t_S,MIN and t_H,MIN for other t_CYCLE values can be interpolated between or extrapolated from the timings at the 3 specified t_CYCLE values.
d. This parameter also applies to a -800 part when operated with t_CYCLE=2.81ns.
e. With V_IL,CMOS=0.5V_CMOS-0.4V and V_IH,CMOS=0.5V_CMOS+0.4V
f. Effective hold becomes t_H4’=t _H4+[PDNXA•64•t_SCYCLE+t_PDNXB,MAX]-[PDNX•256•t _SCYCLE]
if [PDNX•256•t_SCYCLE] < [PDNXA•64•t_SCYCLE+t_PDNXB,MAX]. See Figure 49.
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Version 1.11 Oct. 2000