K4R271669B Datasheet, PDF (16/20 Pages) Samsung semiconductor – 256K x 16/18 bit x 32s banks Direct RDRAMTM

K4R271669B/K4R441869B
Direct RDRAM^™
Timing Characteristics
Table 12: Timing Characteristics
Symbol
t_Q
t_QR, t_QF
t_Q1
t_HR
t_QR1, t_QF1
t_PROP1
t_NAPXA
t_NAPXB
t_PDNXA
t_PDNXB
t_AS
t_SA
t_ASN
t_ASP
Parameter
CTM-to-DQA/DQB output time @ t_CYCLE=2.50ns
CTM-to-DQA/DQB output time @ t_CYCLE=2.81ns
CTM-to-DQA/DQB output time @ t_CYCLE=3.33ns
DQA/DQB output rise and fall times
SCK(neg)-to-SIO0 delay @ C_LOAD,MAX = 20pF (SD read data valid).
SCK(pos)-to-SIO0 delay @ C_LOAD,MAX = 20pF (SD read data hold).
SIO_OUT rise/fall @ C_LOAD,MAX = 20pF
SIO0-to-SIO1 or SIO1-to-SIO0 delay @ C_LOAD,MAX = 20pF
NAP exit delay - phase A
NAP exit delay - phase B
PDN exit delay - phase A
PDN exit delay - phase B
ATTN-to-STBY power state delay
STBY-to-ATTN power state delay
ATTN/STBY-to-NAP power state delay
ATTN/STBY-to-PDN power state delay
Min
-0.260^a
-0.300^a,b
0.350^a,c
0.2
-
2
-
-
-
-
-
-
-
-
-
-
Max
+0.260^a
+0.300^a,b
+0.350^a,c
0.45
10
-
5
10
50
40
4
9000
1
0
8
8
Unit
ns
ns
ns
ns
ns
ns
ns
ns
µs
t_CYCLE
t_CYCLE
t_CYCLE
t_CYCLE
t_CYCLE
Figure(s)
Figure 57
Figure 57
Figure 60
Figure 60
Figure 60
Figure 60
Figure 49
Figure 49
Figure 49
Figure 49
Figure 47
Figure 47
Figure 48
Figure 48
a. t_Q,MIN and t_Q,MAX for other t_CYCLE values can be interpolated between or extrapolated from the timings at the 3 specified t_CYCLE values.
b. This parameter also applies to a -800 part when operated with t_CYCLE=2.81ns.
c. This parameter also applies to a -800 or -711 part when operated with t_CYCLE=3.33ns.
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Version 1.11 Oct. 2000