UPD70F3451GC-UBT-A Datasheet, PDF (971/1191 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

CHAPTER 19 DMA FUNCTIONS (DMA CONTROLLER)
19.3.6 DMA trigger factor registers 0 to 3 (DTFR0 to DTFR3)
The DTFR0 to DTFR3 registers are 8-bit registers that control the DMA transfer start trigger via interrupt requests
from on-chip peripheral I/O.
The interrupt requests set by these registers serve as DMA transfer start factors.
These registers can be read or written in 8-bit or 1-bit units. However, only bit 7 (DFn) can be read or written in 1-
bit units; bits 5 to 0 (IFCn5 to IFCn0) can only be read or written in 8-bit units.
Reset sets these registers to 00H.
Cautions 1. Be sure to follow the steps below when changing the DTFRn register settings.
• When the values to be set to the IFCn5 to IFCn0 bits are not set to the IFCm5 to IFCm0 bits
of another channel (n = 0 to 3, m = 0 to 3, n ≠ m)
<1> Follow steps <3> to <5> when the DCHCn.Enn bit is cleared to 0, and follow steps <2>
to <5> when the Enn bit is set to 1.
<2> Stop the DMAn operation of the channel to be rewritten (DCHCn.INITn bit = 1).
<3> Change the DTFRn register settings. (Be sure to set DFn bit = 0 and change the
settings in the 8-bit manipulation.)
<4> To clear a DMA transfer request, clear the DMA transfer request flag (DTFRn.DFn) to
0.
<5> Enable the DMAn operation (Enn bit = 1).
• When the values to be set to the IFCn5 to IFCn0 bits are set to the IFCm5 to IFCm0 bits of
another channel (n = 0 to 3, m = 0 to 3, n ≠ m)
<1> Follow steps <4> to <6> when the DCHCn.Enn bit is cleared to 0, and follow steps <2>
to <6> when the Enn bit is set to 1.
<2> Stop the DMAn operation of the channel to be rewritten (DCHCn.INITn bit = 1).
<3> Stop the DMAm operation of the channel where the same values are set to the IFCm5
to IFCm0 bits as the values to be used to rewrite the IFCn5 to IFCn0 bits
(DCHCm.INITm bit = 1).
<4> Change the DTFRn register settings. (Be sure to set the DFn bit = 0 and change the
settings in the 8-bit manipulation.)
<5> To clear a DMA transfer request, clear the DMA transfer request flag (DTFRn.DFn) to
0.
<6> Enable the DMAn operation (Enn and Emm bits = 1).
2. An interrupt request from an on-chip peripheral I/O input in the standby mode (IDLE or STOP
mode) is held pending as a DMA transfer start factor. The held DMA start factor is executed
after restoring to the normal operation mode.
3. If the start factor of DMA transfer is changed using the IFCn5 to IFCn0 bits, be sure to set (0)
the DFn bit by instruction immediately after.
User’s Manual U18279EJ3V0UD
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