UPD70F3451GC-UBT-A Datasheet, PDF (420/1191 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT)
(2/2)
TTmECS1 TTmECS0
Valid edge setting of encoder clear signal (TECRm pin)
0
0
Detects no edge (clearing encoder is invalid).
0
1
Detects rising edge.
1
0
Detects falling edge.
1
1
Detects both edges.
TTmEIS1 TTmEIS0 Valid edge setting of encoder input signals (TENCm0, TENCm1 pins)
0
0
Detects no edge (inputting encoder is invalid).
0
1
Detects rising edge.
1
0
Detects falling edge.
1
1
Detects both edges.
Cautions 1. Rewrite the TTmSCE, TTmZCL, TTmBCL, TTmACL, TTmECS1, TTmECS0, TTmEIS1, and
TTmEIS0 bits when the TTmCTL0.TTmCE bit = 0. (The same value can be written to these
bits when the TTmCE bit = 1.) If rewriting was mistakenly performed, clear the TTmCE bit
to 0 and then set these bits again.
2. The TTmECS1 and TTmECS0 bits are valid only when the TTmSCE bit = 0 and the encoder
compare mode is set.
3. The TTmEIS1 and TTmEIS0 bits are valid only when the TTmCTL2.TTmUDS1 and
TTmCTL2.TTmUDS0 bits = 00 or 01.
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User’s Manual U18279EJ3V0UD