UPD70F3451GC-UBT-A Datasheet, PDF (956/1191 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

CHAPTER 18 BUS CONTROL FUNCTION
(7) Write cycle (when data wait state (1 wait) insertion)
T1
T2
TW
T3
CLKOUT (output)
A0 to A7 (output)
AD0 to AD15 (I/O)
Address
Address
Data
ASTB (output)
RD (output) ^H
WR0, WR1 (output)
CS0, CS1 (output)
Note 1
Note 2
WAIT (input)
Notes 1. The levels of these signals are as follows, depending on the access data bus width.
Access Data Bus Width
16 bits
8 bits
WR1
Low level
High level
WR0
Low level
Low level
2. Only the CS space that can be accessed becomes active.
Remarks 1. The circle { indicates the sampling timing.
2. The broken lines indicate the high-impedance state.
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User’s Manual U18279EJ3V0UD