UPD70F3451GC-UBT-A Datasheet, PDF (379/1191 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB)
7.6.6 Free-running timer mode (TABnMD2 to TABnMD0 bits = 101)
In the free-running timer mode, 16-bit timer/event counter AB starts counting when the TABnCTL0.TABnCE bit is
set to 1. At this time, the TABnCCRa register can be used as a compare register or a capture register, depending on
the setting of the TABnOPT0.TABnCCSa bit.
Figure 7-32. Configuration in Free-Running Timer Mode
TABnCCR3
register
(compare)
TABnCCR2
register
(compare)
TABnCCR1
register
(compare)
TABnCCR0
register
(compare)
Internal count clock
EVTBn pin
(external event
count input)
Edge
detector
TIBn0 pin^Note
(capture
trigger input)
Edge
detector
TIBn1 pin^Note
(capture
trigger input)
Edge
detector
TIBn2 pin^Note
(capture
trigger input)
TIBn3 pin^Note
(capture
trigger input)
Edge
detector
Edge
detector
Count
clock
selection
TABnCE
bit
16-bit counter
TABnCCR0
register
(capture)
TABnCCR1
register
(capture)
TABnCCR2
register
(capture)
TABnCCR3
register
(capture)
Output
controller
TOBn3 pin^Note
Output
controller
TOBn2 pin^Note
Output
controller
TOBn1 pin^Note
Output
controller
TOBn0 pin
TABnCCSa bit
(capture/compare
selection)
INTTBnOV signal
0
INTTBnCC3 signal
1
0
INTTBnCC2 signal
1
0
INTTBnCC1 signal
1
0
INTTBnCC0 signal
1
Note Because the capture trigger input pin (TIBnb) and timer output pin (TOBnb) share the same alternate-
function pin, the two functions cannot be used at the same time.
Remark n = 0, 1, a = 0 to 3, b = 1 to 3
User’s Manual U18279EJ3V0UD
377