UPD70F3451GC-UBT-A Datasheet, PDF (747/1191 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

CHAPTER 14 ASYNCHRONOUS SERIAL INTERFACE A (UARTA)
(8) Transfer rate during continuous transmission
During continuous transmission, the transfer rate from the stop bit to the next start bit is usually 2 base clocks
longer. However, timing initialization is performed via start bit detection by the receiving side, so this has no
influence on the transfer result.
Figure 14-14. Transfer Rate During Continuous Transmission
Start bit
Bit 0
FL
FL
1 data frame
Start bit of 2nd byte
Bit 1
Bit 7 Parity bit Stop bit Start bit Bit 0
FL
FL
FL
FLstp
FL
FL
Assuming 1 bit data length: FL; stop bit length: FLstp; and base clock frequency: fUCLK, we obtain the following
equation.
FLstp = FL + 2/fUCLK
Therefore, the transfer rate during continuous transmission is as follows.
Transfer rate = 11 × FL + (2/fUCLK)
14.8 Cautions
When the clock supply to UARTAn is stopped (for example, in IDLE or STOP mode), the operation stops with each
register retaining the value it had immediately before the clock supply was stopped. The TXDAn pin output also holds
and outputs the value it had immediately before the clock supply was stopped. However, the operation is not
guaranteed after the clock supply is resumed. Therefore, after the clock supply is resumed, the circuits should be
initialized by setting the UAnCTL0.UAnPWR, UAnCTL0.UAnRXE, and UAnCTL0.UAnTXE bits to 000.
Remark n = 0 to 2
User’s Manual U18279EJ3V0UD
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