UPD70F3451GC-UBT-A Datasheet, PDF (453/1191 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT)
(2) Operation timing in external event count mode
Caution The use of timer output (TOTm0, TOTm1) is prohibited in the external event count mode.
(a) Operation if TTmCCR0 register is set to 0000H
When the TTmCCR0 register is set to 0000H, the 16-bit counter is repeatedly cleared to 0000H and
generates the INTTTEQCm0 signal each time it has detected the valid edge of the external event count
signal and its value has matched that of the CCR0 buffer register.
The value of the 16-bit counter is always 0000H.
FFFFH
16-bit counter
0000H
TTmCE bit
TTmCCR0 register
0000H
INTTTEQCm0 signal
INTTTEQCm0 signal is generated each time the 16-bit
counter counts the valid edge of the external event count input.
Remark V850E/IF3: m = 1
V850E/IG3: m = 0, 1
(b) Operation if TTmCCR0 register is set to FFFFH
If the TTmCCR0 register is set to FFFFH, the 16-bit counter counts up to FFFFH each time the valid edge
of the external event count signal has been detected. The 16-bit counter is cleared to 0000H in
synchronization with the next count-up timing, and the INTTTEQCm0 signal is generated. At this time, the
TTmOPT0.TTmOVF bit is not set.
FFFFH
16-bit counter
0000H
TTmCE bit
TTmCCR0 register
INTTTEQCm0 signal
FFFFH
External event External event External event
count: 10000H count: 10000H count: 10000H
Remark V850E/IF3: m = 1
V850E/IG3: m = 0, 1
User’s Manual U18279EJ3V0UD
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